mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 7

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

bit for direction control on stream 0 channel 1 and channel 29. When DC bit is set, DSo channel is output from the
FMIC and DSi is input to the FMIC. When DC bit is cleared, the channel directions are reversed.
Timing and Clock Control
The FMIC clock control circuitry contains an on-chip analog PLL (with external loop filter) which is designed to
phase lock to a 4.096 MHz clock. The on-chip VCO runs at eight times this rate yielding a 32 MHz clock which is
divided by two. The resulting 16.384 MHz is used as the internal master clock of the FMIC.
The input to the analog PLL can be selected from among several different sources including, the MVIP C4 clock
which is used as the internal master clock of the FMIC.
The on-chip digital PLL generates a 4.096 MHz clock which is phase locked to an externally generated 8 kHz clock.
The digital PLL state machine is clocked at 16.384 MHz. The digital PLL maintains lock by occasionally dropping or
repeating a 16.384 MHz clock period on the generated 4.096 MHz clock. Consequently, the 4.096 MHz clock has
jitter equal to about 60 ns. If the output of the digital PLL is chosen as the input to the analog PLL, a slow loop filter
with a time constant greater than several 8 kHz frames will smooth out the jitter.
The clock oscillator pins X1 and X2 can be used with an external 16.384 MHz crystal or pin X1 can be used directly
as a clock input with X2 left unconnected. When X1 is used as a clock input, the frequency of the clock can be
selected to be either 16.384 MHz or 8.192 MHz or 4.096 MHz by changing the XCLK_SEL bits in the CLK_CNTL
register.
The overall FMIC state machine from which all timing is derived, is clocked by the 16.384 MHz output of the analog
PLL, the device’s master clock. The state machine controls all timing in the FMIC and has a period equal to one
MVIP frame (8 kHz). This state machine can either free run or synchronize to an 8 kHz source such as the MVIP F0
signal or an external 8 kHz reference.
Refer to Figure 4 - “Clock Control Functional Block Diagram” for further details.
0
O/P
1
2
DSi0
3
. . . . .
I/P
29
Figure 3 - Per-channel Direction Control
30
DC=1 for stream 0 channel 29
DC=0 for stream 0 channel 1
31
Zarlink Semiconductor Inc.
MT90810
FMIC
7
0
1
I/P
2
3
. . . . .
DSo0
29
O/P
Data Sheet
30
31