mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 24

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

JTAG Support
The FMIC JTAG interface is designed to the Boundary-Scan standard IEEE1149.1. The standard specifies a
design-for-testability technique called Boundary-Scan Test (BST). A boundary-scan IC has a shift-register stage or
‘Boundary-Scan Cell’ (BSC) in between the core logic and the I/O buffers adjacent to each I/O pin. The BSCs can
control and observe what happens at each I/O pin of the IC. The operation of the boundary-scan circuitry is
controlled by a Test Access Port (TAP) Controller.
Test Access Port (TAP)
The Test Access Port (TAP) provides access to many test support functions built into the FMIC. It consists of three
input connections and one output connection. The following connections form the TAP:
•
•
2
1
0
Bit
Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK must not interfere with any on-chip clock and thus remain
independent. This permits shifting of test data into or out of the Boundary-Scan register cells concurrently
with the operation of the device without interfering with on-chip logic.
Test Mode Select Input (TMS)
The logic signal (0’s and 1’s) received at the TMS input are interpreted by the TAP Controller to control the
test operations. The TMS signals are sampled at the rising edge of the TCK pulses. When TMS is not driven
from an external source, the test logic perceives a logic 1.
MC
CE
CAB8
Name
Table 22 - Connection Memory High Bits for Local Channels
Message Channel. This bit, when set, will send the eight bits of connection memory
low directly out the corresponding output channel and stream. When the bit is cleared,
the contents of the programmed location in connection memory low act as an address
for the data memory and so determine the source of the corresponding output channels
and stream.
Channel Enable. If the DMA_EN bit in the Control/Status register is set, then this bit
flags the control logic to perform a bidirectional DMA transfer for this input/output
channel pair. When the bit is clear, the DMA transfer for this channel pair is disabled.
If DMA operations are not enabled then this bit must be cleared.
Source Channel Address Bit 8. This bit, together with bits CAB0-7 in connection
memory low, is used to select one of 384 different source input channels for the
connection.
BSC
BOUNDARY -SCAN CELL(BSC)
BSC
Figure 12 - A Typical Boundary-Scan IC
BSC
BSC
CORE LOGIC
Zarlink Semiconductor Inc.
BSC
BSC
MT90810
BSC
BSC
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Description
TEST DATA IN (TDI)
TEST CLOCK (TCK)
TEST DATA OUT (TDO)
TEST MODE
SELECT (TMS)
Data Sheet