mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 26

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

•
The FMIC boundary-scan register contains 84 bits. Bit 0 in Table 24 - “Boundary Scan Register” is the first bit
clocked out. All tristate enable bits are asserted high i.e., a logic 1 enables the corresponding group of
outputs/bidirectionals. Note that clocking all zeros into the scan path register will set all outputs to tristate.
The Bypass Register
The Bypass Register is a single stage shift-register that provides a one-bit path that minimizes the distance
for test data shifting from the FMIC’s TDI to its TDO.
0:11
12:23
24:31
33:40
42:45
47:51
53:54
55:58
59:62
63:70
72:75
76:83
Bits
32
41
46
52
71
Table 24 - Boundary Scan Register
FGB[11:0]
FGA[11:0]
DSo[7:0]
tristate enable for DSo[7:0]
DSi[7:0]
tristate enable for DSi[7:0]
F0, C4, C2, SEC8K
tristate enable for
FRAME, CLK8, CLK4, CLK2, CSTo
tristate enable for ALL output only pins
EX8KA, EX8KB
LDO[3:0]
LDI[3:0]
D[7:0]
tristate enable for D[7:0]
RDY, ERR, DREQ[1:0]
RD, WR, CS, ALE, A[1:0], DACK[1:0]
Zarlink Semiconductor Inc.
MT90810
26
Definition
Data Sheet