mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 25

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

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Instruction Register
In accordance with the IEEE 1149.1 standard, the FMIC uses public instructions listed in Table 23 - “Instruction
Register”. The FMIC JTAG Interface contains a two bit instruction register. Instructions are serially loaded into the
Instruction Register from the TDI when the TAP Controller is in its Shift-IR state. Subsequently, the instructions are
decoded to achieve two basic functions: to select the test data register that may operate while the instruction is
current and to define the serial test data register path that is used to shift data between TDI and TDO during data
register scanning.
Test Data Registers
As specified in the IEEE 1149.1 Standard, the FMIC JTAG interface contains two test data registers:
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I[0:1] Instruction
[00] EXTEST
[01] SAMPLE/PR
[10] BYPASS/TE
[11] BYPASS/NO
The Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a
subsequent section. The received input data is sampled at the rising edge of the TCK pulses. When TDI is
not driven from an external source, the test logic perceives a logic 1.
The Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction
register or a data register are serially shifted out towards the TDO. The data out of the TDO is clocked at the
falling edge of the TCK pulses. When no data is shifted through the cells, the TDO driver is set to an inactive
state.
The Boundary Scan Register
The Boundary-Scan Register consists of a series of Boundary-Scan Cells arranged to form a scan path
around the boundary of the core logic of the FMIC.
ELOAD
ST
TEST
Boundary-Scan
register selected,
Test Enabled
Boundary-Scan
register selected,
Test Disabled
Bypass register
selected,
Test Enabled
Bypass register
selected,
Test Disabled
Table 23 - Instruction Register
This instruction is specifically provided to allow board-level interconnect
testing of opens, bridging errors etc.
When the EXTEST instruction is selected, the on-chip logic is isolated
from the FMIC’s I/O pin such that the value of the I/O pins is determined
by its boundary-scan register. Data for the execution of this instruction
can be preloaded into the boundary-scan register with the
SAMPLE/PRELOAD instruction.
Two functions can be performed by the use of this instruction. It allows a
SAMPLE (‘snapshot’) of the normal operation of the FMIC to be taken for
examination. And, prior to the selection of another test operation, a
PRELOAD can place data values into the latched parallel outputs of the
Boundary-Scan cells. During the execution of the instruction, the on-chip
logic operation is not hampered in any way.
This instruction is used to BYPASS the FMIC while sampling or loading
the data registers in other devices with scan registers in the same serial
register chain. The FMIC is in test mode and the value of it’s I/O pins is
determined by its boundary-scan register.
This instruction is used to BYPASS the FMIC while performing boundary-
scan testing on other devices with scan registers in the same serial
register chain. The FMIC is allowed to function normally. This instruction
is automatically loaded upon reset of the FMIC, as specified in
IEEE1149.1
Zarlink Semiconductor Inc.
MT90810
25
Description
Data Sheet