mt90869ag2 Zarlink Semiconductor, mt90869ag2 Datasheet - Page 80
mt90869ag2
Manufacturer Part Number
mt90869ag2
Description
Flexible 16k Digital Switch F16kdx
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90869AG2.pdf
(84 pages)
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Backplane and Local Output High-Impedance Timing
Note 1: High Impedance is measured by pulling to mid-rail with R
LSTo0 - 31
2.048 Mb/s
4.096 Mb/s
LSTo0 - 31
4.096 Mb/s
1
2
8.192 Mb/s
* CK_int is the internal clock signal of 131.072 MHz
8.192 Mb/s
LSTo0 - 31
LSTi0 - 31
2.048 Mb/s
LSTi0 - 31
LSTi0 - 31
CK_int *
STo delay - Active to High-Z
Output Driver Enable (ODE)
Delay to Active Data
Output Driver Enable (ODE)
Delay to High-Impedance
FP8i
C8i
Characteristic
Ch31
Ch127
Bit0
Bit1
- High-Z to Active
Figure 27 - ST-BUS Local Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s)
1
Ch31
Bit0
Bit0
Ch63
Ch127
Ch63
Bit0
Bit0
0
t
Ch0
LFBOS
Bit7
t
t
LIDS4
LSOD8
t
7
LSOD4
Sym.
t
t
t
LSOD2
ODE
ODZ
t
t
Ch0
Bit7
DZ
ZD
t
t
LSIS8
LIDS8
t
LSIH8
Ch0
Bit7
t
LIDS2
Zarlink Semiconductor Inc.
Ch0
Bit6
6
Min.
MT90869
t
LSIS4
t
LSIH4
Ch0
Bit7
L
80
Ch0
Bit5
Typ.
= 1k//1k potential divider, with timing corrected for C
5
Ch0
Bit7
Ch0
Bit6
Max.
Bit6
Ch0
15
14
t
LSIS2
4
4
Ch0
Bit4
4
t
LSIH2
Unit
ns
ns
ns
ns
s
Bit3
Ch0
3
Bit5
Ch0
R
R
R
L
L
L
Ch0
Bit5
=1K, C
=1K, C
=1K, C
Ch0
Bit2
Test Conditions
2
L
L
L
Ch0
Bit6
=50pF, See Note 1
=50pF, See Note 1
=50pF, See Note 1
Ch0
Bit1
1
Bit6
Ch0
Data Sheet
L
Bit4
Ch0
.
Bit4
Ch0
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