mt90869ag2 Zarlink Semiconductor, mt90869ag2 Datasheet - Page 65

• Manufacturer Part Number: mt90869ag2
• Description: Flexible 16k Digital Switch F16kdx
• Manufacturer: Zarlink Semiconductor

13.11.4
Address 00CBh
Backplane BER Start Receive Register defines the Input Stream and the Start Channel in which the BER sequence
shall be received. The BBSRR register is configured as follows:
13.11.5
Address 00CCh
Backplane BER Count Register contains the number of counted errors. This register is read only. The BBCR
register is configured as follows:
13.12
13.12.1
Address 00CDh to 00ECh
Thirty-two Local Input Bit Rate Registers allow the bit rate for each individual stream, to be set to 2, 4, 8 or 16 Mb/s.
The LIBRR registers are configured as follows:
15-14
(for n=0 to 31)
13-9
15-0
8-0
Bit
Bit
LIBRn
15-2
1-0
Local Bit Rate Registers
BBRCA(8:0)
BBRSA(4:0)
Backplane BER Start Receive Register (BBSRR)
Backplane BER Count Register (BBCR)
Reserved
BBC(15:0)
Local Input Bit Rate Registers (LIBRR0-31)
Name
Name
Reserved
LIBR(1:0)
Name
Table 39 - Backplane BER Start Receive Register (BBSRR) Bits
Reset
Reset
Table 40 - Backplane BER Count Register (BBCR) Bits
Table 41 - Local Input Bit Rate Register (LIBRRn) Bits
0
0
0
0
Reserved.
Backplane BER Receive Stream Address Bits
The binary value of these bits defines the backplane input stream that
receives the BER data.
Backplane BER Receive Channel Address Bits
The binary value of these bits define the backplane input start channel in
which the BER data will be received.
Reset
Backplane Bit Error Rate Count
The binary value of these bits define the Backplane Bit Error count.
0
0
Reserved
Local Input Bit Rate
Zarlink Semiconductor Inc.
MT90869
65
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Data Sheet