m21130 Mindspeed Technologies, m21130 Datasheet - Page 20
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m21130
Manufacturer Part Number
m21130
Description
68 X 68 3.2 Gbps Crosspoint Switch With Input Equalization
Manufacturer
Mindspeed Technologies
Datasheet
1.M21130.pdf
(34 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
m21130-11
Manufacturer:
Mindspee
Quantity:
11
21130-DSH-001-B, 3/27/03
Table 14. Register Summary
Notes:
1. D[7] ... D[0] represent the internal bus which is mapped to the registers in both the serial and parallel mode.
2. Blank registers bits are undefined and should be set to 0 unless otherwise noted.
Address
EB
EC
ED
EE
C3
E0
E1
E2
E3
E4
E5
E6
E7
E8
EF
00
01
02
43
80
81
82
F0
R/W In#Data to Out#0
R/W In#Data to Out#1
R/W In#Data to Out#2
R/W In#Data to Out#67
Enable In/Out Channel #0
Enable In/Out Channel #1
Enable In/Out Channel #2
Enable In/Out Channel #67
prbs power
prbs control
prbs RX error count
prbs pattern length
prbs pattern [7:0]
prbs pattern [15:8]
prbs pattern [22:16]
xSET mode
software xSET
I/O enable
core control
slope control internal
slope control pad
software reset
chip revision
Register Name
(1)(2)
68 x 68 3.2 Gbps Crosspoint Switch with Input Equalization
rxerr[7]
pat[15]
pat[7]
rev[7]
d7
Mindspeed Technologies™
muxdrv
rxerr[6]
pat[14]
pat[22]
pat[6]
rev[6]
D[6]
D[6]
D[6]
D[6]
d6
coredrv[1]
rxerr[5]
pat[13]
pat[21]
pat[5]
rev[5]
D[5]
D[5]
D[5]
D[5]
d5
coredrv[0]
pwr_trig
rxerr[4]
txlen[1]
pat[12]
pat[20]
pat[4]
rev[5]
D[5]
D[5]
D[5]
D[5]
d4
rxerr[3]
txlen[0]
pat[11]
pat[19]
ifdrv[1]
pwr_tx
pat[3]
rev[3]
D[3]
D[3]
D[3]
D[3]
d3
en_individ
rxerr[2]
ioen[2]
ioen[2]
ioen[2]
ioen[2]
pwr_rx
pat[10]
pat[18]
Ifdrv[0]
pat[2]
rxcirc
rev[2]
D[2]
D[2]
D[2]
D[2]
d2
M21130
paddrv[1]
clkdrv[1]
en_refs
rxlen[1]
rxerr[1]
pat[17]
ioen[1]
ioen[1]
ioen[1]
ioen[1]
xset[1]
Page 20 of 34
en_tx
pat[1]
pat[9]
en_in
rev[1]
rst_tx
D[1]
D[1]
D[1]
D[1]
d1
paddrv[0]
clkdrv[0]
rxlen[0]
rxerr[0]
ioen[0]
ioen[0]
ioen[0]
ioen[0]
pat[16]
en_out
xset[0]
srst[0]
en_rx
rst_rx
pat[0]
pat[8]
en_lp
rev[0]
D[0]
D[0]
D[0]
D[0]
d0