m21130 Mindspeed Technologies, m21130 Datasheet - Page 16

• Manufacturer Part Number: m21130
• Description: 68 X 68 3.2 Gbps Crosspoint Switch With Input Equalization
• Manufacturer: Mindspeed Technologies

21130-DSH-001-B, 3/27/03
Figure 7
On each falling edge of SCLK, the 10-bits consisting of SB = 1, OP = 1, and the 8-bit ADDR are written to the serial input shift register
of the M21130. On the first rising edge following the address LSB, the SB and 8-bits of the DATA are shifted out on SDO. The first bit
output on SDO for a read operation is always 0.
On a Write cycle, any bits that follow the expected number of bits are ignored, and only the first 16-bits following SB and OP are used.
On a Read cycle, any extra clock cycles will result in the repeat of the data LSB. An invalid SB or OP renders the operation undefined.
The falling edge of xCS always resets the serial operation for a new Read or Write cycle.
for the serial programming interface.
Table 12. Serial Interface Timing – Specified at Recommended Operating Conditions
Figure 7. Serial Read Mode
SCLK
Notes:
1. Edge rate in the high edge-rate mode.
SDO
xCS
SDI
Symbol
t
t
t
t
t
t
t
wclk
t
ens
t
t
rdd
illustrates the serial Read mode timing diagram. To initiate a read sequence, xCS goes low before the falling edge of SCLK.
dw
rds
dh
clk
ds
cs
ch
t
t
Tens
r
f
1
Data width
Data hold time
Data setup time
Enable setup time
Chip select setup time
Chip select hold time
Read data output delay
Read data valid
SCLK period width
SCLK minimum low duration
Output rise time
Output fall time
rd
Tdw
a7
a6
Tds
Item
a5
68 x 68 3.2 Gbps Crosspoint Switch with Input Equalization
a4
a3
Mindspeed Technologies™
a2
Tdh
a1
Notes
—
—
—
—
—
—
—
—
—
—
a0
1
1
X
0
Minimum
Tclk-15
d7
X
20
20
—
—
5
5
5
2
2
1
5
Twclk
d6
X
Table 12
d5
X
Typical
Tclk
—
—
—
—
—
—
—
—
—
—
—
—
d4
X
Trdd
contains the timing specifications
d3
X
Maximum
Trds
Tclk - 2
Tclk - 5
d2
X
15
—
—
—
—
—
—
—
4
4
d1
Tcs
X
M21130
Page 16 of 34
d0
X
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Tch
1