m21130 Mindspeed Technologies, m21130 Datasheet - Page 17

• Manufacturer Part Number: m21130
• Description: 68 X 68 3.2 Gbps Crosspoint Switch With Input Equalization
• Manufacturer: Mindspeed Technologies

M21130
68 x 68 3.2 Gbps Crosspoint Switch with Input Equalization
Switch Function Details
Introduction
Many functions of the crosspoint switch can be accessed through hardware pins or through software via the serial/parallel interface. In
some cases, both software and hardware can access the same function. This section describes the various functions in detail.
Information on individual registers is listed in
Table 14
and
Table
15.
Input Equalization
To reduce jitter caused by inter-symbol-interference (ISI), input equalization (IE) circuitry is integrated into each input channel of the
M21130. ISI is typically generated when the signal is routed through long PCB traces, cables, or backplane connectors. The IE circuit
for each input channel is enabled by default. The IE for each channel can be individually enabled/disabled through the “I/O Individual
Channel Enable” registers, addresses 80–C3h. Bit 3 of this register is used to enable or disable the IE. Note that bit 2 of register EBh
must be set to “1” to individually enable/disable the IE for a particular channel.
Switch Setting
The previous section described the details of the programming interface for register writing, reading, and configuring the switch.
Table 14
lists the allowable addresses for the crosspoint switch. The input channel selection registers are mapped to
ADDR=00h…43h. ADDR 00h is assigned to output channel 0, ADDR 01h to output channel 1, and ADDR 43h to output channel 67.
DATA associated with ADDR are 00h…43h and are mapped to the input channel that is routed to the selected output. For example if
ADDR=05h and DATA=02h, then output #5 gets input #2. To Read the current configuration of a particular output channel, the
selected channel is specified by ADDR and the resulting DATA is the input channel # routed to the selected output. The Next Switch
State (NSS) in the ICL cannot be read back if it differs from the ACL. The default state after power on is channel 0 broadcast to all
outputs (all registers cleared). Note that bit D[7] of the register data (regardless of the serial or parallel interface option) is undefined
for a READ and ignored for a WRITE.
Input/Output Enable
The xInDis and xOutDis pins will disable the inputs and outputs, respectively. Setting xInDis=L globally disables all inputs and,
conversely, setting xOutDis=L globally disables all outputs. Hardware disable has priority. If not hardware disabled (xInDis/
xOutDis=H), the I/O enable register (ADDR=EBh) provides control for all off, all on, or individual control. If individual control is
selected, the 68 registers for I/O individual channel enable (ADDR=80h…C3h) determine the input/output buffer status. For the
outputs, a disabled state implies turning off the output stage current source to save power. With built-in pull-up resistors, both positive
and negative outputs will default to the high logic state when disabled.
If an output is enabled, but the input channel routed to the output is disabled, the input stage current source will be off and the input
signal will not drive to the output and the positive and negative outputs will be in an indeterminate state. The default state is the I/O
enable register set to all input/outputs off, and the I/O individual channel enable registers set to all inputs/outputs off.
The I/O enable register (ADDR=EBh) determines the global state of the input/output registers. If D[2]=0, the two LSB determine if the
inputs/outputs are all off (global). If D[2]=1, the two LSB are ignored and the I/O individual channel enables take priority.
xRST/xTEST
The reset function provides a power-on reset and a general reset to default settings for all registers. The xTest pin is used by
Mindspeed Technologies for internal testing and should be tied to V
for normal operation. A hardware reset should be issued to the
DD
M21130 after initial power up. To issue a hardware reset to the M21130, the xRST pin should be pulled low for a minimum of 20 ns and
then pulled to a high state. This will reset all registers to their default settings. Both the ICL and ACL are cleared resulting in the switch
core set to broadcast channel 0 to all channels. PRBS Tx and Rx are disabled and error flags are cleared. A hardware reset should be
sent to the M21130 after power-up.
If xTest=L after reset, then channel 0 is broadcast to all outputs and all inputs/outputs are enabled regardless of the I/O enable and I/
O individual channel enable registers’ contents. These features are used for Mindspeed Technologies internal die testing. For normal
operation, xTest=H and xRst =H. Issuing a software reset requires two consecutive Writes to the software reset register (ADDR=EFh)
21130-DSH-001-B, 3/27/03
Mindspeed Technologies™
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