mt9160bsr1 Zarlink Semiconductor, mt9160bsr1 Datasheet - Page 12

• Manufacturer Part Number: mt9160bsr1
• Description: 5v Multi-featured Phone Codec With Programmable U/a Law Companding
• Manufacturer: Zarlink Semiconductor

Register Summary
Note: Bits marked "-" are reserved bits and should be written with logic "0"
Address
Gain Control Register 1
RxINC: When high, the receive path nominal gain is set to 0 dB. When low, this gain is -6.0 dB.
TxINC: When high, the transmit nominal gain is set to 15.3 dB. When low, this gain is 6.0 dB.
07y
00
01
02
03
04
05
06
RxFG
Receive Gain
Setting (dB)
n
(default) 0
= Receive Filter Gain bit n
RxINC
PDFDI
RxINC RxFG
-1
-2
-3
-4
-5
-6
-7
Bit 7
CEN
C
D
-
-
-
7
7
7
RxFG
PDDR
6
Bit 6
DEN
C
D
RxFG
-
-
-
2
6
6
0
0
0
0
1
1
1
1
2
RxFG
Table 2 - V Multi-Featured Codec Register Map
2
5
RxFG
Bit 5
RST
1
RxFG
D8
C
D
-
-
-
RxFG
5
5
0
0
1
1
0
0
1
1
1
4
1
0
RxFG
RxFG
Zarlink Semiconductor Inc.
Bit 4
MT9160B/61B
TxINC
A/m
C
D
0
1
0
1
0
1
0
1
-
-
-
-
4
4
3
0
0
TxFG
ANALOG
12
T
TxFG
Smag/
TxINC
2
ITU-T
PCM/
Bit 3
x
Mute
C
D
-
-
2
3
3
Transmit Gain
n
Setting (dB)
= Transmit Filter Gain bit n
(default) 0
TxFG
1
1
2
3
4
5
6
7
R
TxFG
loopen
1
STG
CSL
Bit 2
x
Mute
C
D
TxFG
-
ADDRESS = 00h WRITE/READ VERIFY
2
2
2
0
2
2
0
TxFG
T
STG
CSL
Bit 1
x
TxFG
C
D
Bsel
-
-
1
1
0
0
0
0
1
1
1
1
1
1
1
2
DrGain
R
TxFG
STG
CSL
Bit 0
x
TxFG
C
D
Power Reset Value
Bsel
-
0
0
0
0
1
1
0
0
1
1
0
0
0
1000 0000
1
Gain Control
Gain Control
Path Control
Description
Data Sheet
C-Channel
D-Channel
Loop Back
Register 1
Register 2
Register 1
Register 2
TxFG
Register
Register
Control
Control
0
1
0
1
0
1
0
1
0