mt9160bsr1 Zarlink Semiconductor, mt9160bsr1 Datasheet - Page 11

• Manufacturer Part Number: mt9160bsr1
• Description: 5v Multi-featured Phone Codec With Programmable U/a Law Companding
• Manufacturer: Zarlink Semiconductor

MT9160B/61B
Data Sheet
SSI Mode
The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input
signal (CLOCKin), a framing strobe input (STB) and the MT9161B provides a delayed framing strobe output
(STBd). The frame strobe must be synchronous with, and eight cycles of, the bit clock. A 4.096 MHz master clock is
also required for SSI operation if the bit clock is less than 512 kHz. The timing requirements for SSI are shown in
Figures 12 & 13.
In SSI mode the MT9160B/61B supports only B-Channel operation. The internal C and D Channel registers used in
ST-BUS mode are not functional for SSI operation. The control bits TxBSel and RxBSel, as described in the ST-
BUS section, are ignored since the B-Channel timeslot is defined by the input STB strobe. Hence, in SSI mode
transmit and receive B-Channel data are always in the channel defined by the STB input.
The data strobe input STB determines the 8-bit timeslot used by the device for both transmit and receive data. This
is an active high signal with an 8 kHz repetition rate.The MT9161B provides a delayed strobe pulse (STBd) which
occurs 4 frames after the initial strobe goes low and is held high for the duration of 8 pcm bits.
SSI operation is separated into two categories based upon the data rate of the available bit clock. If the bit clock is
512 kHz or greater then it is used directly by the internal MT9160B/61B functions allowing synchronous operation.
If the available bit clock is 128 kHz or 256 kHz, then a 4096 kHz master clock is required to derive clocks for the
internal MT9160B/61B functions.
Applications where Bit Clock (BCL) is below 512 kHz are designated as asynchronous. The MT9160B/61B will re-
align its internal clocks to allow operation when the external master and bit clocks are asynchronous. Control bits
CSL2, CSL1 and CSL0 in Control Register 2 (address 04h) are used to program the bit rates.
For synchronous operation data is sampled, from Din, on the falling edge of BCL during the time slot defined by the
STB input. Data is made available, on Dout, on the rising edge of BCL during the time slot defined by the STB input.
Dout is tri-stated at all times when STB is not true. If STB is valid and PDDR is set, then quiet code will be
transmitted on Dout during the valid strobe period. There is no frame delay through the FDI circuit for synchronous
operation.
For asynchronous operation Dout and Din are as defined for synchronous operation except that the allowed output
jitter on Dout is larger. This is due to the resynchronization circuitry activity and will not affect operation since the bit
cell period at 128 kb/s and 256 kb/s is relatively large. There is a one frame delay through the FDI circuit for
asynchronous operation. Refer to the specifications of Figures 13 & 14 for both synchronous and asynchronous
SSI timing.
PWRST/Software Reset (Rst)
While the MT9160B/61B is held in PWRST no device control or functionality is possible. While in software reset
(Rst=1, address 03h) only the microport is functional. Software reset can only be removed by writing the Rst bit low
or by performing a hardware PWRST. While the Rst bit is high, the other bits in Control Register 1 are held low and
cannot be reprogrammed. Therefore to modify Control Register 1 the Rst bit must first be written low, followed by a
2nd write operation which writes the desired data. This avoids a race condition between clearing the reset bit and
the writing of the other bits in Control Register 1.
After a Power-up reset (PWRST) or software reset (Rst) all control bits assume their "Power Reset Value" default
states; µ-Law coding, 0 dB Rx and 6dB Tx gains and the device powered up in SSI mode 2048 kb/s operation with
Dout tri-stated while there is no strobe active on STB. If a valid strobe is supplied to STB, then Dout will be active,
during the defined channel.
To attain complete power-down from a normal operating condition, write PDFDI = 1 and PDDR = 1 (Control
Register 1, address 03h) or set the PWRST pin low.
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Zarlink Semiconductor Inc.