mt9160bsr1 Zarlink Semiconductor, mt9160bsr1 Datasheet
mt9160bsr1
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mt9160bsr1 Summary of contents
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... Copyright 1999-2005, Zarlink Semiconductor Inc. All Rights Reserved. 5 Volt Multi-Featured Codec (MFC) MT9160BE MT9160BS MT9160BN MT9160BSR MT9160BN1 MT9160BSR1 MT9160BS1 Description The MT9160B/61B incorporates a built-in Filter/Codec, gain control and programmable sidetone path as well as on-chip anti- alias filters, reference voltage and bias source. The device supports both ITU-T and sign-magnitude A-Law and µ ...
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... PIN PDIP Figure 2 - Pin Connections Description /2) volts is available at this pin for biasing external DD SSA, SSA, SSD . Logically OR’ed with A/µ register bit. DD This input signal is used to select the device for microport 2 Zarlink Semiconductor Inc. Data Sheet MT9161BE/BS/BN VBias VRef ...
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... B-Channel select (ST-BUS mode), C&D channel control/access, law control, digital interface programming and loopback. Optionally the device may be used in a controllerless mode utilizing the power-on default settings. MT9160B/61B Description ® and National Semiconductor Microwire 3 Zarlink Semiconductor Inc. Data Sheet ® specifications. These ...
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... To facilitate this the V Ref -TxFG and RxFG 0 2 -STG control bits located in Gain Control Register 2 (address 01h Zarlink Semiconductor Inc. Data Sheet Bias is also brought to an external pin so that it to analog Bias and V Ref Bias -RxFG control bits, respectively. ...
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... Default Bypass -6 dB Side-tone -9. (3.32 dB steps) -11 dB Transmit Transmit Gain Gain -0. 8.93 dB 8.42 dB INTERNAL TO DEVICE Figure 3 - Audio Gain Partitioning 5 Zarlink Semiconductor Inc. Data Sheet A-Law 1010 1010 1101 0101 0101 0101 0010 1010 HSPKR + -8. -2.05 dB Handset Receiver Receiver 75 W (150 W) ...
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... bit - Read/Write 3 bits - Addressing Data X 4 bits - Unused 6 Zarlink Semiconductor Inc. Data Sheet 4 COMMAND/ADDRESS ...
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... Flexible Digital Interface A serial link is required to transport data between the MT9160B/61B and an external digital transmission device. The MT9160B/61B utilizes the ST-BUS architecture defined by Zarlink Semiconductor but also supports a strobed data interface found on many standard Codec devices. This interface is commonly referred to as Simple Serial ...
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... When 1, ST-BUS D-channel data ( bits/frame depending on the state of the D8 bit) is shifted into/out of the D- channel (READ/WRITE) register. When 0, the receive D-channel data (READ) is still shifted into the proper register while the DSTo D-channel timeslot and IRQ outputs are tri-stated (default). MT9160B/61B 8 Zarlink Semiconductor Inc. Data Sheet ...
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... TxBSel and RxBSel (Control Register 1, address 03h) are used for this purpose valid transmit path has been selected then the timeslot output on DSTo is tri-stated (see PDFDI and PDDR control bits, Control Register 1 address 03h). MT9160B/61B 9 Zarlink Semiconductor Inc. Data Sheet ...
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... V VI VII VIII III Di-bit Group Transmit D-Channel Power-up reset to 1111 1111 10 Zarlink Semiconductor Inc. Data Sheet Microport Read/Write Access n+2 n+3 n+4* II III Power-up reset to 1111 1111 t =500 nsec max pullup Reset coincident with ...
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... Dout tri-stated while there is no strobe active on STB valid strobe is supplied to STB, then Dout will be active, during the defined channel. To attain complete power-down from a normal operating condition, write PDFDI = 1 and PDDR = 1 (Control Register 1, address 03h) or set the PWRST pin low. MT9160B/61B 11 Zarlink Semiconductor Inc. Data Sheet ...
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... TxFG = Transmit Filter Gain bit Zarlink Semiconductor Inc. Data Sheet Bit 1 Bit 0 Description TxFG TxFG Gain Control Register 1 STG STG Gain Control Register DrGain Path Control Mute T Bsel ...
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... STG STG STG ADDRESS = 02h WRITE/READ VERIFY - - - - DrGain Zarlink Semiconductor Inc. Data Sheet Power Reset Value XXXX X000 Power Reset Value XX00 0000 ...
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... When high, the receive B2 channel is functional in ST-BUS mode. When low, the receive B1 channel is functional in ST-BUS mode. Not used in SSI mode. MT9160B/61B ADDRESS = 03h WRITE/READ VERIFY _ TxBsel RxBsel TxMute RxMute Zarlink Semiconductor Inc. Data Sheet Power Reset Value 0000 0000 ...
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... ITU Bit Clock rate (kHz) CLOCKin (kHz) N/A 4096 128 4096 256 4096 512 512 1536 1536 2048 2048 4096 4096 15 Zarlink Semiconductor Inc. Data Sheet Power Reset Value 0000 0010 0 Mode ST-BUS SSI SSI SSI SSI SSI (default) SSI ...
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... A/D and D/A circuits as well as through the normal transmit A/D Din HSPKR +/- Dout M +/- PCM/ANALOG = 1 Figure 8 - Loopback Signal Flows 16 Zarlink Semiconductor Inc. Data Sheet ADDRESS = 05h WRITE/READ Power Reset Value 1111 1111- write XXXX XXXX - read ADDRESS = 06h WRITE/READ Power Reset Value ...
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... Converter Lin MT8972 DNIC Z T Lout 10.24 MHz Figure 9 - Digital Telephone Set 17 Zarlink Semiconductor Inc. Data Sheet 330 W VBias + + 0 VBias Single-ended Amplifier M+ M- 150 DSTi DSTo F0i C4b M+ M- ...
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... VBias 0 0 A/m/IRQ CS SCLK DATA1 DATA2 DATA2 Motorola Mode only From Digital Phone Twisted Pair C4 Clock Input Figure 10 - Delayed Frame Pulse of First MT9161B Signalling Second MT9161B Zarlink Semiconductor Inc. MT9160B/61B ) From Subscriber AV= 5-10 Line Interface ...
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... DD V 4.5 V IHC 0.5 ILC Sym. Min. Typ. Max DDC1 I 7.0 10 DDFT 19 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units - ± ° 150 750 mW Units Test Conditions ×C Units Test Conditions µA Outputs unloaded, Input ...
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... 0. ‡ Min. Typ. Max. Units 4095.6 4096 4096.4 kHz 20 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions Max. Load = 10 kΩ load 0.9 See Note ...
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... D 360 AX D 750 DX 380 130 750 PSSR 37 PSSR1 40 PSSR2 35 PSSR3 40 21 Zarlink Semiconductor Inc. Data Sheet for µ-Law and 0 dBm0 = A - 3.14 dB rms Lo3.14 Units Test Conditions µ-Law Vp-p Vp-p A-Law Both at Codec Transmit filter gain=0 dB setting. dB TxINC = 0* dB TxINC = 1* @1020 Hz ...
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... D 240 AR D 750 DR 380 130 750 Zarlink Semiconductor Inc. Data Sheet for µ-Law and 0 dBm0 = A - 3.14 dB rms Lo3.14 Units Test Conditions µ-Law Vp-p Vp-p A-Law dB DrGain=0, RxINC =1* dB DrGain=0, RxINC =0* dB DrGain=1, RxINC =1* dB DrGain=1, RxINC =0* @ 1020 Hz ...
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... D ‡ Sym. Min. Typ. Max. V 2.90 IOLH 1. Zarlink Semiconductor Inc. Data Sheet Test Conditions RxINC = 0* RxINC = 1* M± inputs to HSPKR± outputs 1000 Hz at STG2=1 Test Conditions across HSPKR± pF each pin: HSPKR+, HSPKR- % 300 ohms load across HSPKR± (tol-15%), VO≤ ...
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... DSTiS t 50 DSTiH 1 bit cell C4P C4H C4L DSToD t t DSTiH DSTiS t F0iH Clock Periods Figure 11 - ST-BUS Timing Diagram 24 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions pF, 1 kΩ load ...
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... DSTBF t 50 DOZL t 50 DOZH t 50 DOLZ t 50 DOHZ DIS t 50 DIH 25 Zarlink Semiconductor Inc. Data Sheet Test Conditions ns BCL=4096 kHz to 512 kHz ns BCL=4096 kHz ns BCL=4096 kHz ns Note 1 ns Note 1 ns Note Note 1 ns Note =150 pF, R ...
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... DATA DATA1 DATA DATA +500ns-T j +(n- DATA DATA +500ns+T j +(n- DATA 26 Zarlink Semiconductor Inc. Data Sheet t DOLZ t t SSH DOHZ t DSTBF t DSTBR t ENWD (CMOS I/O) DD Max. Units Test Conditions ns BCL=128 kHz ns BCL=256 kHz 600 ns T +600 ns C =150 pF, R ...
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... ODD t 500 1000 CYC t 250 500 CH t 250 500 CL t 200 CSSI t 200 CSSM t 100 CSH t 100 OHZ 27 Zarlink Semiconductor Inc. Data Sheet T j (CMOS I/O) DD Units Test Conditions 150 pF 150 pF ...
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... CSSI CS t CSSM t CH SCLK IDH t IDS 2.0V 0.8V MT9160B/61B DATA INPUT DATA OUTPUT t CYC CYC DATA OUTPUT DATA INPUT Figure 14 - Microport Timing 28 Zarlink Semiconductor Inc. Data Sheet 90% 2.0V HiZ 0.8V 10% Intel t ODD Mode = 0 2.0V 0.8V t OHZ 2.0V 0.8V t CSH 2.0V Motorola Mode = 00 0.8V t ODD 90% 2.0V HiZ 0.8V 10% ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...