ml86v7667 Oki Semiconductor, ml86v7667 Datasheet - Page 5

• Manufacturer Part Number: ml86v7667
• Description: Ntsc/pal Digital Video Decoder
• Manufacturer: Oki Semiconductor

PIN DESCRIPTIONS
OKI Semiconductor
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
７
1
2
3
4
5
6
8
9
STATUS1
STATUS2
STATUS3
STATUS4
RESET_L
LPFOUT
TEST [2]
TEST [1]
TEST [0]
ADVDD
ADGND
Symbol
SLEEP
PGND
AGND
AGND
DGND
PVDD
AVDD
AVDD
DVDD
SCAN
VREF
REFP
REFN
VIN1
VIN2
SDA
SCL
LPF
CM
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
PLL power supply
Center frequency setting pin. Connect to the PGND pin when not
used.
Analog PLL loop filter connection pin. Connect to the PGND pin
when not used.
See the sample circuit provided in the User's Manual.
PLL ground
Digital power supply in the analog block.
Digital ground in the analog block.
Analog ground
Composite-1 input
Connect this pin to AGND when not used.
Composite-2 input
Connect this pin to AGND when not used.
Analog power supply
A/D C reference voltage (high)
A/D C reference voltage (middle)
A/D C reference voltage (low)
Analog ground
Not used. Open
Analog power supply
Digital power supply
Digital ground
Not used. Should be fixed to "0".
Sleep signal input. “0”: Normal operation, “1”: Sleep operation
Reset signal input. “0”: Reset, 1: Normal operation
Reset after power ON.
Not used. Should be fixed to "0".
Not used. Should be fixed to "0".
Not used. Should be fixed to "0".
I
Putt this pin into the “0” state when not used.
I
STATUS output pin 1. Selected by the internal register.
Default HVALID
STATUS output pin 2. Selected by the internal register.
Default VVALID
STATUS output pin 3. Selected by the internal register.
Default ODD/EVEN
STATUS output pin 4. Selected by the internal register.
Default CSYNC
2
2
C bus data input/output pin. Pulled up by a 4.7 k resistor.
C bus clock input. Put this pin into the “0” state when not used.
Description
Should be left pen.
Should be left pen.
Should be left pen.
PEDL86V7667-00
ML86V7667
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