ml86v7667 Oki Semiconductor, ml86v7667 Datasheet - Page 11

• Manufacturer Part Number: ml86v7667
• Description: Ntsc/pal Digital Video Decoder
• Manufacturer: Oki Semiconductor

Chr ominance Block
This block decodes chroma data to Cb/Cr data and performs level adjustment and color adjustment. To eliminate
unnecessary bands, this block first passes data through a bandpass filter (bypass is possible) and then through an
ACC correction circuit to maintain a stable chroma level, before performing UV decoding. The result of the UV
decoding is passed through a low-pass filter and output as a chrominance signal.
# Related registers: $12/CHRCA, $13/CHRCB
Output Block
The output block performs output timing adjustment, picture sizing, output format conversion and other types of
output conversion.
OKI Semiconductor
Digital ACC Function
Hue Adjust Function
Pixel Count Correction Function
The digital ACC is the gain adjustment for the chrominance signal output level. Adjustment is automatically
performed by the digital ACC (Auto Chrominance Control), but the adjustment can also be set manually by
using an internal register to set digital MCC (Manual Chrominance Control). In the digital ACC mode, the
burst level is compared with a reference value to determine the amplification rate of the chrominance level. The
default is automatically adjusted to sync level 40IRE, but the level can also be adjusted in an internal register.
Separate U/V level adjustment is also possible.
# Related registers: $12/CHRCA, $14/ACCC, $15/ACCRC
The function for adjusting hue.
Hues can be adjusted by setting the HUE register.
# Related register: $16/HUE
This function uses the internal FIFO to correct the total number of pixels in a line. It corrects the 1-line
sampling error generated when in asynchronous sampling mode or PLL synchronization is lost, and fixes the
pixel count for a line within the active screen. Refer to Active Pixel Timing for more on the pixel count for one
line.
# Related registers $03/MRD[7:6], $19/OMRB
The internal FIFO can be set in the through mode by register $03/MRD[7:6].
MRD[7:6] = "00" : FIFO-1 mode
MRD[7:6] = "01" : FIFO-2 mode * (default)
MRD[7:6] = "10" : FIFO through mode
MRD[7:6] = "11" : Undefined
The standard value of the pixel count per horizontal (H) line is output by the internal FIFO.
The standard value of the pixel count per horizontal (H) line is output by the internal FIFO.
This mode is different from the FIFO-1 mode in the internal processing method.
The FIFO-2 mode is more effective than the FIFO-1 mode for non-standard signals.
This is the mode in which the value of the decoded result of an input signal is output
without correcting the pixel count by the internal FIFO.
PEDL86V7667-00
ML86V7667
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