ml86v7667 Oki Semiconductor, ml86v7667 Datasheet - Page 12

• Manufacturer Part Number: ml86v7667
• Description: Ntsc/pal Digital Video Decoder
• Manufacturer: Oki Semiconductor

Synchr onization Block
This block controls the sync signals for internal operation, output sync signals, and the timing for each block.
Synchronization detection levels, output timing, and various other functions can be adjusted by the registers listed
below.
OKI Semiconductor
Output Format Conversion Function
PLL Function
This function converts the output data to the desired output format.
The following output formats are possible.
# Related registers: $00/MRA, $01/MRC
# Related registers: $03/MRD, $04/SYDR, $05/HSYT, $06/STHR, $07/VSTHR, $08/HSDL, $09/HVALT,
The digital PLL circuit generates an operating clock synchronized with the horizontal sync signals of the video
signals. With the input of a 25 MHz or 32 MHz standard clock, the double-speed sampling clock for each mode
is provided as a line lock clock and used as the system clock.
The asynchronous sampling mode, which uses an asynchronous clock directly, can be used without using PLL.
# Related registers: $20/PLLR1, $21/PLLR2
In the PLL mode, a double-speed line lock clock is generated by setting the operating mode.
PLLR1[7]=0
PLL ON
Register $20/PLLR[7]
—
PLL ON/OFF
Y/CbCr 8-bit multiplex(i) 4:2:2
ITU-R BT.656 (i) 4:2:2
$0A/VVALT1, $0B/VVALT2, $12/CHRCA, $13/CHRCB, $17/BBHC, $18/OMRA,
$1A/OMRC, $1B/OMRD
PLLR1[7]=1
PLL OFF
Output mode
(i): interlace
-
PLLR1[6]=0
32MHz
Input Clock Settings
PLL reference clock
—
Output Formats
PLLR1[6]=1
Control pin
MRA[0]=0
MODE[2]
Register
(Pin 57)
25MHz
[0]
[1]
—
Input clock
Sampling clock input according to
the operating mode
MRA[0]=1
MRA[7:6]
Register
Register
(See the table on the next page.)
*[01]
[00]
Asynchronous clock
Register
MRC[5]
—
0
0
PEDL86V7667-00
ML86V7667
12/31