tea5761uk NXP Semiconductors, tea5761uk Datasheet - Page 15

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tea5761uk

Manufacturer Part Number
tea5761uk
Description
Tea5761uk Low-voltage Single Chip Fm-stereo Radio
Manufacturer
NXP Semiconductors
Datasheet

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Fig 5. I
(1) Interrupt events that occur outside of the region A to B
(2) The blocking of interrupts is marked by the region A to B
(3) Interrupt events that occur between A and B
(4) All interrupt mask bits are cleared after the interrupt flag and mask registers are read.
(5) Software writes to the mask register and enables the required mask bits. Any flags currently set will then trigger a hardware interrupt.
(6) Pin INTX is set HIGH (inactive) after the interrupt flag and mask registers are read.
mask bits are set.
B
B
in period A to B
2
1
2
C-bus interrupt sequence, read and write operation
data
interrupt event
interrupt flag bit
interrupt mask bit
INTX
is when only the INTFLAG register is read and a stop condition is received (only INTFLAG is read, so only this will be cleared).
is when both registers are read and hence cleared; this is terminated by either an acknowledge or stop bit.
read access
S
address
1
device
or B
2
, so after period A to B
R ack
(1)
A
0R data
INTFLAG
ack
1
2
or B
the flag goes to logic 1.
B
1
1R data
2
set their respective flags after the mask bits are cleared. This means that in this diagram an interrupt event occurred
INTMSK
(2)
1
or B
1
or B
ack
2
set their respective flag bits in the normal way immediately and can thus trigger a hardware interrupt if the
B
2
2
, depending on the actual read cycle.
(3)
(4)
(6)
data
ack
write access
S
address
device
W ack
0W data
INTMSK
ack
(5)
(5)
1W data
FRQSETMSB
ack
FRQSETLSB
2W data
ack
001aab464
P

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