wm8152scds-v Wolfson Microelectronics plc, wm8152scds-v Datasheet - Page 16

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wm8152scds-v

Manufacturer Part Number
wm8152scds-v
Description
Single Channel 16-bit Cis/ccd Afe With 4-bit Wide Output
Manufacturer
Wolfson Microelectronics plc
Datasheet
WM8152
w
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, V
input video.
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted
instead.
If VRLCEXT = 1, V
If VRLCEXT = 0, V
V
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST
The resultant signal V
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain,
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 16-bit unsigned number, with input range configured by
PGAFS[1:0].
where the ADC full-scale range, V
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP.
RLCSTEP
is the step size of the RLC DAC and V
V
V
V
V
V
D
D
D
D
D
if D
if D
1
1
VRLC
2
3
1
1
1
2
2
[15:0] = INT{ (V
[15:0] = INT{ (V
[15:0] = INT{ (V
[15:0] = D
[15:0] = 65535 – D
1
1
[15:0] < 0
[15:0] > 65535 D
=
=
=
=
=
VRLC
VRLC
1
1
[15:0]
is added to the Offset DAC output.
is an externally applied voltage on pin VRLC/VBIAS.
is the output from the internal RLC DAC.
V
V
(V
V
V
IN
IN
1
2
3
3
3
RLCSTEP
+ {260mV ∗ (DAC[7:0]-127.5) } / 127.5 ..................... Eqn. 4
∗ [0.78+(PGA[7:0]*7.57)/255] ................................... Eqn. 5
/V
/V
/V
- V
- V
D
1
FS
FS
FS
[15:0]
1
1
RESET
VRLC
[15:0] = 0
[15:0] = 65535
) ∗ 65535} + 32767 PGAFS[1:0] = 00 or 01 ...... Eqn. 6
) ∗ 65535}
) ∗ 65535} + 65535 PGAFS[1:0] = 10 ............... Eqn. 8
FS
∗ RLCV[3:0]) + V
= 2.5V
.................................................................... Eqn. 2
................................................................... Eqn. 1
RLCBOT
RLCBOT
PGAFS[1:0] = 11 ............... Eqn. 7
(INVOP = 0) ...................... Eqn. 9
(INVOP = 1) ...................... Eqn. 10
is the minimum output of the RLC DAC.
................................. Eqn. 3
RESET
PD, Rev 4.3, August 2008
, is subtracted from the
Production Data
16

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