wm8152scds-v Wolfson Microelectronics plc, wm8152scds-v Datasheet - Page 15

• Manufacturer Part Number: wm8152scds-v
• Description: Single Channel 16-bit Cis/ccd Afe With 4-bit Wide Output
• Manufacturer: Wolfson Microelectronics plc

Production Data
ADC INPUT BLACK LEVEL ADJUST
OVERALL SIGNAL FLOW SUMMARY
CALCULATING OUTPUT FOR ANY GIVEN INPUT
w
The output from the PGA should be offset to match the full-scale range of the ADC (V
negative-going input video signals, a black level (zero differential) output from the PGA should be
offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input
signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11.
Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential
input voltage gives mid-range ADC output).
Figure 12 represents the processing of the video signal through the WM8152.
Figure 12 Overall Signal Flow
The INPUT SAMPLING BLOCK produces an effective input voltage V
difference between the input video level V
difference between the input video level V
optionally set via the RLC DAC.
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the
black level of the input signal towards 0V, producing V
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,
outputting voltage V
The ADC BLOCK then converts the analogue signal, V
The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D
The following equations describe the processing of the video and reset level signals through
the WM8152. The values of V
setup. The PGA value is written first to set the input Voltage range, the Offset DAC is then
adjusted to compensate for any Black/Reset level offsets and finally the RLC DAC value is
set to position the reset level correctly during operation.
Note: Refer to WAN0123 for detailed information on device calibration procedures.
V
V
V
VRLCEXT=1
IN
RESET
VRLC
CDS = 0
CDS = 1
DAC
RLC
SAMPLING
VRLCEXT=0
BLOCK
INPUT
+
V
3
RLCSTEP
.
-
V
*RLCV[3:0] + V
1
OFFSET DAC
BLOCK
+ +
1
Offset
DAC
V
A = 0.78+(PGA[7:0]*7.57)/255
2
V
and V
260mV*(DAC[7:0]-127.5)/127.5
2
RLCBOT
BLOCK
PGA
PGA gain
X
3
IN
are often calculated in reverse order during device
and the input reset level V
V
IN
3
analog
and the voltage on the VRLC/VBIAS pin, V
2
.
+65535 if PGAFS[1:0]=10
3
+32767 if PGAFS[1:0]=0x
+0
, to a 16-bit unsigned digital output, D
x (65535/V
if PGAFS[1:0]=11
ADC BLOCK
FS
V
V
V
CDS, VRLCEXT,RLCV[3:0], DAC[7:0],
PGA[7:0], PGAFS[1:0] and INVOP are set
by programming internal control registers.
CDS=1 for CDS, 0 for non-CDS
)
IN
RESET
VRLC
is VINP voltage sampled on video sample
RESET
is voltage applied to VRLC pin
is VINP sampled during reset clamp
PD, Rev 4.3, August 2008
D
digital
. For non-CDS this is the
1
1
. For CDS, this is the
D2 = D1 if INVOP = 0
D2 =65535-D1 if INVOP = 1
OUTPUT
INVERT
BLOCK
FS
WM8152
= 2.5V). For
D
OP[3:0]
2
Range
1
.
VRLC
2.
15
,