msm7654 Oki Semiconductor, msm7654 Datasheet - Page 24

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msm7654

Manufacturer Part Number
msm7654
Description
Ntsc/pal Digital Video Encoder
Manufacturer
Oki Semiconductor
Datasheet

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1Semiconductor
OUTPUT FORMAT
The timing conforms to the ITU-R BT.624-4 standard.
In the NTSC operation mode, the existence/non-existence of setup level is selected by setting of
internal regsiters.
Data level on the DAC input terminal:
When the contents of 100% luminance order color bar are input into the encoder, the input level
is as follows.
NTSC Composite Signal (Setup 7.5IRE)
DAC data Lumi (IRE)
Note that images may be disturbed in the case below.
If a scan mode of the encoder moves from the non-interlace operation to interlace operation when the
phase between the VSYNC_L input timing and the HSYNC_L input timing is not 0H and 1/2H or if
disturbed signals corresponding to this situation are input, the vertical sync period differs from the
standard value and normal interlace scan cannot be performed. In this state, the interlace scan is
restored to a normal state by system resetting or resetting with Master/Slave switching.
945
775
718
623
565
476
418
335
324
266
224
114
4
130.8
–20.0
–40.0
89.5
72.3
61.8
45.7
35.2
20.0
18.0
100
7.5
0.0
Composite Waveform (NTSC)
NTSC Composite Signal (Setup 7.5)
White
Yellow
Cyan
Green
Magenta
Red
Blue
Black
MSM7654
24

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