msm7654 Oki Semiconductor, msm7654 Datasheet

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msm7654

Manufacturer Part Number
msm7654
Description
Ntsc/pal Digital Video Encoder
Manufacturer
Oki Semiconductor
Datasheet

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MSM7654
OKI Semiconductor
NTSC/PAL Digital Video Encoder
GENERAL DESCRIPTION
The MSM7654, which is a digital video encoder supporting NTSC/PAL formats, converts digital
image data to an analog video signal.
The encoder can receive the digital image or RGB digital image signals conforming to ITU-R
BT.601 as an input signal.
The encoder can output simultaneously the composite video and S-video signals, and it can also
output the RGB analog signal by switching.
The encoder can control luminance (Y) signal output levels of the composite video and S-video
signals.
FEATURES
• Video signal system: NTSC/PAL
• Scanning system: interlaced/noninterlaced (NTSC : 262 lines/PAL : 312 lines)
• Input digital level: conforms to ITU-R BT.601 (CCIR601)
• Input-output timing: conforms to ITU-R BT.656 or ITU-R BT.624-4
• Input signal sampling ratio : Y:Cb:Cr = 4:2:2 or 4:1:1/R:G:B = 8:8:8
• Supported input interface
• Pixel frequency (Sampling frequency) :
• Output format
• Master or slave operation (slave operation only in ITU-R BT.656 mode)
• Internal 3ch 10-bit DAC
• 3-bit title/graphics can be displayed (only for composite and S-video signals)
• Color bar function
• I
• Brightness level adjust of 100% to 68.75% (only for composite and S-video signals)
• GENLOCK control
• 3.3 V single power supply (each I/O pin is 5 V tolerable)
• Package
· ITU-R BT.656
· YCbCr format (8-bit input)
· ITU-R BT.601 (8-bit (Y) + 8-bit (CbCr) input)
· RGB (24-bit input)
· 12.272727 MHz (24.545454 MHz) : NTSC Square Pixel
· 13.5 MHz (27 MHz) : NTSC/PAL ITU-R BT.601
· 14.318182 MHz (28.636364 MHz) : NTSC 4Fsc
· 14.75 MHz (29.5 MHz) : PAL Square Pixel
· Selectable composite & S-video or RGB
· 37.5
64-pin plastic QFP (QFP64-P-1414-0.80-BK)
2
C-bus host interface function
driving capability
(Product name: MSM7654GA)
Issue Date: Jan. 8, 2004
FEDL7654-03
1

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msm7654 Summary of contents

Page 1

... MSM7654 NTSC/PAL Digital Video Encoder GENERAL DESCRIPTION The MSM7654, which is a digital video encoder supporting NTSC/PAL formats, converts digital image data to an analog video signal. The encoder can receive the digital image or RGB digital image signals conforming to ITU-R BT.601 as an input signal. ...

Page 2

... Semiconductor APPLICATIONS • Video CD • Video game equipment • Electronic still cameras • Video filing systems • Video cameras • Videophones • Multimedia equipment • Video printers • Videoconferencing systems • Scanners • Video graphics boards • Monitoring systems MSM7654 2 ...

Page 3

RESET_L OLC OLR YUV Color OLG Generator OLB Y Level Converter YD[7:0] U Level Converter Prologue Block V Level CD[7:0] Converter RGB YUV BD[7:0] Converter VSYNC_L HSYNC_L CSYNC_L Sync Generator & Timing Controller BLANK_L CLKX2 MS GENLOCK RGBMODE Black & ...

Page 4

... PIN CONFIGURATION (TOP VIEW SDA 2 SCL 3 RGBMODE 4 MODE3 5 MODE2 6 MODE1 7 MODE0 GENLOCK 10 CSYNC_L 11 VSYNC_L 12 HSYNC_L 13 BLANK_L DGND 16 64-Pin Plastic QFP MSM7654 OUTSEL 46 CLKX2 45 TENB 44 RESET_L 43 FOUT 42 BD7(B7) 41 BD6(B6) 40 BD5(B5) 39 BD4(B4) 38 BD3(B3) 37 BD2(B2) 36 BD1(B1) 35 BD0(B0 DGND 4 ...

Page 5

... System reset pin. Input pin for testing. Normally fixed to "0". Internal pull-down. The user cannot use this pin. Clock input pin. MSM7654 0001 : NTSC 27 MHz YCbCr 0011 : NTSC 28.64 MHz 4Fsc 0110 : NTSC 12.27 MHz 1001 : PAL 27 MHz YcbCr 1101 : PAL 13 ...

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... Analog color chrominance signal output pin or B (Blue) signal output pin. 3.3 V analog power supply. Analog composite signal output pin or G (Green) signal output pin. Analog GND. Analog luminance signal output pin or R (Red) signal output pin. 3.3 V analog power supply. Digital GND. MSM7654 6 ...

Page 7

... 3 3 Vrefex Ta = 25˚C Riadj (*2) 192.5  R 37.5 L and recommendable for adjusting the output MSM7654 Rating Unit –0.3 to +4.5 V –0.3 to +4.5 –0 800 mW –55 to +150 °C Typ. Max. Unit 3.3 3.6 V 3.3 3 ˚C — ...

Page 8

... I DDSM RGBMODE = "1" SDAV Low level SDAI During Acknowledge O Vrefin — — R — — L SINL — SDNL — MSM7654 = 3.3 V ±0 3.3 V ±0 Typ. Max. Unit — — V — 0.8 V — — — 0.4 V — +10 mA — 250 mA — ...

Page 9

... Fclk NTSC Square Pixel ITU-R BT.601/656 t — — — — — — — D2 MSM7654 = 3.3 V ±0 3.3 V ±0 Min. Typ. Max. Unit — 29.5 — MHz — 28.636364 — MHz — 24.545454 — MHz — 27.0 — ...

Page 10

... BLANK_L, YD, CD, BD, MS, RGBMODE, MODE, OLR, OLG, OLB, OLC, OUTSEL (Input) GENLOCK (Input) 2) Output Delay Time CLKX2 (Input) HSYNC_L, VSYNC_L, CSYNC_L, GENLOCK (Output) FOUT (Output 1/Fclk CLKX2 Input Timing T = 1/Fclk CLKX2 t D1 valid data t D2 Output Timing MSM7654 10 ...

Page 11

... Rpull_up = 4 ACK t t C_SCL 2 C-bus Input/Output Basic Timing Reset AC Characteristics ( 70°C, DV Symbol Condition t — Reset Timing MSM7654 = 3.3 V ±0 3.3 V ±0 Min. Typ. Max. 200 — — 100 — — 100 — — 40 — — ...

Page 12

... This block generates luminance and chrominance signals from overlay color signals OLR, OLG and OLB. The control signal (register CR0[3:1]) controls the output content and output level. The output content of overlay or color bar is selected with register CR0[3] and the output level of 100%, 75%, 50%, or 25% is selected with register CR0[2:1]. MSM7654 12 ...

Page 13

... This block converts digital video signals to analog video signals with a 10-bit accuracy and outputs them. Since the analog output pins (YA, CVBSO, CA) are current outputs, these pins should be connected to external resistors. See "Analog output reference circuit in APPLICATION CIRCUIT EXAMPLE" for resistance values standard of Phillips Corporation. MSM7654 13 ...

Page 14

... Two types of input level are available by setting of internal register MR1[5]. Digital Level 235 16 Format 1 Input RGB signal level 1 Digital Level 100% White level 240(112) 128(0) Black Level 16(–112) Digital Level 100% White level Black Level MSM7654 C data Input chrominance signal level 255 0 Format 2 Input RGB signal level 2 14 ...

Page 15

... Y/8bit CbCr input RGB input Cb1 Y1 Cr1 Y2 Cb3 Y3 Cr3 Y4 Cb5 Y5 Cr5 Y6 4:2:2 sampling at 8bit YCbCr input Cb1 Y1 Cr1 Cb5 Y5 Cr5 Y6 Invalid data 4:1:1 sampling at 8bit YCbCr input MSM7654 Y6 Cr5 Y6 Cr5 ...

Page 16

... The write attribute of a register does not match "X" which is the 8th bit (LSB) of the slave address ("X" because this LSI is write only). 262.5 lines 262 lines 312.5 lines 312 lines Data 0 A ..... Description MSM7654 Data ...

Page 17

... Relationship Between Blank Signal and Input Image Data The blank signal is generated by the ITU-R BT.656 standard input data. The input image data is valid when the blank signal is "H". Cb0 Y00 Cr0 Y01 Cb1 Y10 Cr1 Y11 VALID DATA Input timing MSM7654 EAV(1st) EAV(2nd) EAV(3rd) EAV(4th) don't care 17 ...

Page 18

... Cb0, Y00, Cr0, Y01, Cb1, Y10, Cr1, Y11.... 4T CLKX2 4T CLKX1 63T CLKX1 (63T CLKX1 ) (4T CLKX1 ) 127T CLKX1 (142T CLKX1 ) 711T CLKX1 (702T CLKX1 ) 136T CLKX1 (146T CLKX1 ) 8'h10 Y00 Y01 Y10 Y11 8'h80 Cb0 Cr0 Cb1 Cr1 1H MSM7654 1/2H 20T CLKX1 (20T CLKX1 ) 8'h10 8'h80 18 ...

Page 19

... STA In slave mode Operation mode STA CLKX2 250 ITU-R BT.601 NTSC 280 ITU-R BT.601 PAL 266 4 Fsc NTSC 228 Square pixel NTSC 306 Square pixel PAL MSM7654 don't care period. ACT STA STA CLKX2 260 290 276 238 316 19 ...

Page 20

... Input Timing when BLANK_L is Input CLKX2 BLANK_L YD CD, BD Invalid Data Invalid Data Cb0 Y00 t STA Cb0 Invalid Data Invalid Data Y0 Invalid Data Cb0 t START Y0 Cb0 MSM7654 Valid Data Cr0 Y01 Cb1 Y10 t ACT Y00 Cr0 Y01 Cb1 Valid Data Y1 Y2 Cr0 Cb1 t ACT Y1 Y2 ...

Page 21

... Output timing 1 of internal synchronization, HSYNC_L, VSYNC_L, and CSYNC_L VSYNC_L HSYNC_L CSYNC_L YA 523 G (with SYNC) 523 Output timing 2 of internal synchronization HSYNC_L, VSYNC_L, and CSYNC_L t D1 524 525 524 525 MSM7654 ...

Page 22

... If the encoder detects the VSYNC_L falling edge between 1/4H and 1/2H (not including 1/ 2H), it judges information with HSYNC_L and VSYNC_L as an even field and normally operates. (2) If the encoder detects the VSYNC_L falling edge between 1/2H and 3/4H (including 1/2H), it judges information with HSYNC_L and VSYNC_L as an even field and normally operates. VSYNC_L HSYNC_L -1/4H 0H 1/4H 1/4H 1/2H 3/4H MSM7654 22 ...

Page 23

... If the number of lines is equal to the standard value, the contents of output signals per line are normal. • If the number of lines is smaller than the standard value, the first equalizing pulse period is shorter. MSM7654 Front Porch The front porch period is longer than when the normal HSYNC_L signal is input ...

Page 24

... NTSC Composite Signal (Setup 7.5IRE) Composite Waveform (NTSC) DAC data Lumi (IRE) 945 130.8 775 100 718 89.5 623 72.3 565 61.8 476 45.7 418 35.2 335 20.0 324 18.0 266 7.5 224 0.0 114 –20.0 4 –40.0 NTSC Composite Signal (Setup 7.5) Yellow Green Red White Cyan Magenta MSM7654 Black Blue 24 ...

Page 25

... NTSC chrominance (C) signal output C Waveform (NTSC) DAC data Lumi (IRE) 858 63 836 59 754 44 622 20 512 0 402 –20 270 –44 188 –59 166 –63 NTSC C Signal Output (Setup 7.5) White Cyan Yellow Green Yellow Green Cyan Color Burst MSM7654 Magenta Blue Red Black Red Magenta Blue 25 ...

Page 26

... NTSC S-Video Signal (Setup 0IRE) • Luminance (Y) signal output Composite Waveform (NTSC) DAC data Lumi (IRE) 959 133.3 775 100 713 88.6 611 70.1 548 58.7 452 41.3 389 29.9 335 20.0 287 11.4 224 0 114 –20.0 4 –40.0 NTSC Composite Signal (Setup 0) Yellow Green Red White Cyan Magenta MSM7654 Black Blue 26 ...

Page 27

... DAC data Lumi (IRE) 860 63.2 837 59.0 758 44.7 622 20 512 0 402 –20 266 –44.7 187 –59.0 164 –63.2 White Cyan Yellow NTSC Y Signal Output (Setup 0) Yellow Green Cyan Color Burst NTSC C Signal Output (Setup 0) MSM7654 Magenta Blue Green Red Black Red Magenta Blue 27 ...

Page 28

... Semiconductor PAL Composite Signal Composite Waveform (PAL) DAC data Lumi (IRE) 972 133.3 792 100.0 728 88.5 627 70.1 564 58.7 468 41.2 405 29.9 359 21.5 304 11.4 241 0.0 123 –21.5 4 –43.0 Yellow Green White Cyan Magenta PAL Composite Signal MSM7654 Red Black Blue 28 ...

Page 29

... C Waveform (PAL) DAC data Lumi (IRE) 860 63.2 837 59.1 759 44.8 630 21.5 512 0 394 –21.5 265 –44.8 187 –59.1 164 –63.2 White Cyan Yellow PAL Y Signal Output Yellow Green Cyan Color Burst PAL C Signal Output MSM7654 Magenta Blue Green Red Black Red Magenta Blue 29 ...

Page 30

... Whether or not the Sync signal is added to the G signal is determined by setting of register CR0[6]. (CR0[6] = "0": No Sync is added, CR0[6] = "1": Sync is added) R Signal 510 0 G Signal (no Sync) 510 0 G Signal (Sync) 717 207 0 B Signal 510 0 RGB Signal (Output Level Setting: 0-510) MSM7654 30 ...

Page 31

... Semiconductor 2) Output level setting: 32-470 (MR1[ Signal 470 32 G Signal (no Sync) 470 32 G Signal (Sync) 677 239 0 B Signal 470 32 RGB Signal (Output Level Setting: 32-470) MSM7654 31 ...

Page 32

... Burst relative –180° to B-Y axis Burst relative 180° to B-Y axis Output timing (Interlaced NTSC) MSM7654 ...

Page 33

... First equalizing pulse period (3H) B Vertical synchronization period (3H) C Second equalizing pulse period (3H) D Burst pause period E Vertical blanking period (20H) Odd field (Even field 6,259.5 to 262. 17,259.5 to 262.5H Output timing (Interlaced NTSC) MSM7654 Period 259.5 to 262. ...

Page 34

... Continuous odd • even fields 261 to 262H MSM7654 Period 261 to 6H 261 to 17H 34 ...

Page 35

... Output timing (Interlaced PAL) Field 1,5 Field 2,6 311 to 312.5H 311 to 312. 2. 2. 6,310 to 312. 5.5,308.5 to 312. 22.5,311 to 312. 22.5,311 to 312.5H Output timing (Interlaced PAL) MSM7654 ...

Page 36

... Continuous odd • even fields MSM7654 Period 311 to 312H 1 to 2.5H 2 311 to 6H 311 to 22H 36 ...

Page 37

... CLKX1 CLKX1 CLKX1 32T 369T 63T CLKX1 CLKX1 CLKX1 33T 387T 68T CLKX1 CLKX1 CLKX1 28T 332T 58T CLKX1 CLKX1 CLKX1 35T 403T 69T CLKX1 CLKX1 CLKX1 MSM7654 1/2H 429T CLKX1 432T CLKX1 455T CLKX1 390T CLKX1 472T CLKX1 37 ...

Page 38

... CLKX1 CLKX1 CLKX1 36T 75T 135T CLKX1 CLKX1 CLKX1 31T 65T 116T CLKX1 CLKX1 CLKX1 34T 82T 155T CLKX1 CLKX1 CLKX1 MSM7654 t Total dots/1H 838T 858 CLKX1 844T 864 CLKX1 889T 910 CLKX1 762T 780 CLKX1 922T 944 CLKX1 38 ...

Page 39

... CLKX1 CLKX1 CLKX1 CLKX1 197T 278T 359T 440T CLKX1 CLKX1 CLKX1 CLKX1 251T 347T 443T 539T CLKX1 CLKX1 CLKX1 CLKX1 MSM7654 Red Blue Black 572T 661T 750T 858T CLKX1 CLKX1 CLKX1 CLKX1 582T 670T 757T 864T CLKX1 CLKX1 ...

Page 40

... ITU-R BT.656) MR0[3:0] "0000" Slave mode (ITU-R BT.656) 0 Slave mode (Slave) Other than "0000" (specified mode other than ITU-R BT.656) "0000" Slave mode (ITU-R BT.656) 1 Master mode Other than "0000" (specified mode other than ITU-R BT.656) MSM7654 Operation mode Operation mode 40 ...

Page 41

... FOUT T values in slave mode depend on pixel rates. The following table lists the T fout pixel rate. Input interface ITU-R BT.656 YCbCr (8bit) YCbCr (16bit) RGB 1 CLKX2 1 CLKX2 1/2H T fout T fout 1/2H T fout 5 CLKX2 9 CLKX2 9 CLKX2 or 10 CLKX2 9 CLKX2 or 10 CLKX2 MSM7654 values to each fout 41 ...

Page 42

... An external pin cannot output pulses. 0 Output mode GENLOCK ON with MR1[1] resets the subcarrier (GENLOCK ON) phase but its reset timing is not output. An external pin cannot output pulses. 1 GENLOCK OFF does not reset the subcarrier Output mode (GENLOCK OFF) phase and its reset timing is not output. MSM7654 42 ...

Page 43

... The subcarrier phase, however, cannot be reset if the GENLOCK pin is fixed high. (1) Input Timing (Slave mode) CLKX2 GENLOCK (input) CLKX1 (Internal signal) Genlock flag (Internal signal) HSYNC_L (Input) VSYNC_L (Input) T gen GENLOCK Input Timing MSM7654 43 ...

Page 44

... VSYNC_L GENLOCK Field 4 CVBSO 260 261 262 HSYNC_L VSYNC_L GENLOCK CLKX2 VSYNC_L (output) GENLOCK 263 263 263 263 CLKX2 4th field (NTSC) or 8th field (PAL) GENLOCK Output Timing MSM7654 ...

Page 45

... Cb0 Y00 Cr0 Y01 Cb1 Y10 Cr1 VALID DATA VALID DATA VALID DATA VALID DATA Invalid Data Invalid Data Invalid Data Invalid Data Cb0 t STA MSM7654 Y11 EAV(1st) EAV(2nd) EAV(3rd) EAV(4th) don't care Valid Data Y00 Cr0 Y01 Cb1 Y10 4 CLKX2 45 ...

Page 46

... NTSC 24.52 MHz Square Pixel 0011 : NTSC 28.64 MHz 4Fsc 0101 : NTSC 13.5 MHz YCbCr 0110 : NTSC 12.27 MHz 0111 : NTSC 14.32 MHz 1000 : PAL ITU-R BT.656 1001 : PAL 27 MHz YcbCr 1010 : PAL 29.5 MHz Square Pixel 1101 : PAL 13.5 MHz 1110 : PAL 14.75 MHz 1111 : invalid MSM7654 Description 46 ...

Page 47

... Master/Slave MR1 [2] INTERLANCE MR1 [1] Genlock Control 01 MR1 [0] Genlock Select MSM7654 Description Black level setup Note : Valid in NTSC mode only *0 : Black level 0IRE 1 : Black level 7.5IRE Non-standard signal input mode switching *0 : Corresonds to standard signal only 1 : Corresponds to standard and non-standard signals. (The field ...

Page 48

... CR0 [0] Sampling ratio Sampling ratio control *0 : 4:2 4:1:1 CR1 [3:0] Luminance Adjusting luminance level of input image Level data *0000 : 100.00% 0001 : 96.875% 0010 : 93.750% 0011 : 90.675% 0100 : 87.500% 0101 : 84.375% 0110 : 81.250% 0111 : 78.125% 1000 : 75.000% 1001 : 71.875% 1010 : 68.750% MSM7654 Description 48 ...

Page 49

... The following shows the characteristics when the clock frequency is 27 MHz. 0 –20 –40 –60 –80 –100 0 2 (Note) The characteristics of these filters are based on design data Frequency [MHz Frequency [MHz] Up Sampling Filter Frequency Characteristic MSM7654 ...

Page 50

... The characteristics of these filters are based on design data. Trap Filter (for NTSC) Frequency Characteristics Frequency [MHz] Trap Filter (for PAL) Frequency Characteristics Frequency [MHz] MSM7654 ...

Page 51

... W load, the analog output circuit should use 75 W resistors. If the YA, CA and CVBSO pins are terminated with 37.5 W load, an operational amplifier is not used 3 3.3 V 3.3 V MSM7654 DGND AGND CLKX2 3.6 mH 150 W 150 W 164 pF 164 pF MSM7654 XV Typ. 1.25 V REF 3 0 COMP LPF LPF CVBSO R1 R1 ...

Page 52

... The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM7654 (Unit: mm) Package material Epoxy resin ...

Page 53

... OPERATING CONDITIONS” section. • Removed the description for (*3) at the bottom on this page. “Note .....switching” has been added the 24 24 “Slave Mode” section. MSM7654 Description 53 ...

Page 54

... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2004 Oki Electric Industry Co., Ltd. MSM7654 54 ...

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