msm7654 Oki Semiconductor, msm7654 Datasheet - Page 21

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msm7654

Manufacturer Part Number
msm7654
Description
Ntsc/pal Digital Video Encoder
Manufacturer
Oki Semiconductor
Datasheet

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SYNC SIGNALS (VSYNC_L, HSYNC_L) I/O TIMING
By setting the external terminal MS or internal register, this function enables either operation in
the master mode in which the sync signals HSYNC_L and VSYNC_L are internally generated or
operation in the slave mode in which the encoder operates by using the external HSYNC_L and
VSYNC_L (See "SETTINGS OF EACH MODE" for switching between master mode and slave
mode). The field is judged by using the generated HSYNC_L and VSYNC_L.
¡ Semiconductor
Master Mode
Output timing of HSYNC_L and VSYNC_L in master mode is as follows.
VSYNC_L
HSYNC_L
CSYNC_L
YA
G (with SYNC)
CLKX2
HSYNC_L
VSYNC_L
CSYNC_L
Output timing 1 of internal synchronization, HSYNC_L, VSYNC_L, and CSYNC_L
Output timing 2 of internal synchronization HSYNC_L, VSYNC_L, and CSYNC_L
523
523
524
524
525
525
t
D1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
t
D1
17
17
MSM7654
18
18
21

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