msm9405 Oki Semiconductor, msm9405 Datasheet - Page 26

• Manufacturer Part Number: msm9405
• Description: Irda Communication Controller
• Manufacturer: Oki Semiconductor

¡ Semiconductor
• DSR: DMA Mode Select Register (Address = 7h)
the system is reset, all bits of DSR are set to "0".
The DSR (DMA Mode Select Register) is used to select the DMA mode for the MSM9405. When
DSR[1-2]
DSR[3-7]
DSR Bit
DSR[0]
DSR
7
DMA_EN (DMA Mode Enable): This bit determines whether the DMA is to be used. The initial value
is set to "0".
When "1" is written to this bit, DSR[1-2] (DMA_SL
MSM9405 enters the DMA transfer standby mode. (DREQ is asserted when the DREQ assert
condition is met.)
If DMA_EN = "0", DSR[1-2] (DMA_SL
performed. (DREQ is not asserted even if the DREQ assert condition is met.)
DMA_SL (DMA Select): These bits are used to select the method of interfacing with DMAC.
These bits are not used.
DSR
DMA_SL
6
0
0
1
1
DSR
1
5
DSR
DMA_SL
4
0
1
0
1
DSR
0
3
DSR
2
0
, DMA_SL
DREQ becomes active low and DACK becomes active high.
When the RD signal becomes active while DACK is active,
the DMA read cycle (MemoryÆM9405) is selected. When
the WR signal becomes active while DACK is active, the
DMA write cycle (M9405ÆMemory) is selected. While
DACK is being asserted, address "0" (TDR/RDR) is
accessed regardless of the status of A
DREQ becomes active high and DACK becomes active low.
When the WR signal becomes active while DACK is active,
the DMA read cycle (MemoryÆM9405) is selected. When
the RD signal becomes active while DACK is active, the
DMA write cycle (M9405ÆMemory) is selected. While
DACK is being asserted, address "0" (TDR/RDR) is
accessed regardless of the status of A
DREQ becomes active low and DACK becomes active high.
DACK is disabled.
DREQ becomes active high and DACK becomes active low.
DACK is disabled.
Description
DSR
1
1
) setting is disabled and DMA transfer is not
0
DSR
, DMA_SL
0
1
) setting is enabled and the
DMA_EN ("1": DMA mode)
DMA_SL
DMA_SL
Not Used
Function
0
1
(DMA Select 0)
(DMA Select 1)
0
0
to A
to A
3
3
.
.
MSM9405
26/30