msm9405 Oki Semiconductor, msm9405 Datasheet - Page 20

• Manufacturer Part Number: msm9405
• Description: Irda Communication Controller
• Manufacturer: Oki Semiconductor

¡ Semiconductor
• LSR: Line Status Register (Read Only) (Address = 3h)
the system is reset, all bits of the LSR are set to "0". This register is for read only and cannot be
written.
The LSR (Line Status Register) indicates various statuses of the MSM9405 that is running. When
LSR[2-7]
LSR bit
LSR[0]
LSR[1]
LSR
7
TOUT (FIFO Timeout): When time-out occurs in the FIFO during receiving, this bit is set to "1".
When received data is read from the FIFO, TOUT is set to "0".
IR_DET (SIR Pulse detect) : This bit is set to "1" when a pulse having a width of t
upon receiving). It is set to "0" when the CPU reads the LSR.
FLV (FIFO Level): These bits indicate the number of data items in the FIFO with a value of 0 to 32.
LSR
6
LSR
5
LSR
4
LSR
3
LSR
2
LSR
Description
1
LSR
0
TOUT (Timeout = "1")
IR_DET (SIR Pulse detect = "1")
FLV (Byte number in FIFO)
spw
(SIR pulse width
MSM9405
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