msm9405 Oki Semiconductor, msm9405 Datasheet - Page 14

• Manufacturer Part Number: msm9405
• Description: Irda Communication Controller
• Manufacturer: Oki Semiconductor

¡ Semiconductor
when the following time-out occurs even if the received data is below the receiving threshold
level:
the register address assigned from 0h through Ch. Various setting options are provided for each
register to allow optimum communication.
Time-out
The MSM9405 outputs an interrupt request or DMA request depending on the register setting
The condition causing time-out in MIR or FIR mode is:
The condition causing time-out in SIR or Extended SIR mode is:
Register Map
The MSM9405 contains 14 registers, of which 13 are available. Each register can be selected with
The registers are listed below. The register table is given on the next page.
At least 1-byte data is in the receiving FIFO and 69.5 ms has passed after data is written from
the receiving shift register to the FIFO. During this period, the CPU or DMA controller does
not read the FIFO data.
At least 1-byte data is in the receiving FIFO and time (Tout) has passed after data is written
from the receiving shift register to the FIFO. During this period, the CPU or DMA controller
does not read the FIFO data.
Tout = 4 ¥ 8 ¥ 1/baud rate
baud rate: Transfer rate (2.4 to 115.2 kbps)
A
3
Ah
Ah
Bh
Bh
Ch
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
9h
0h
Fh
-A
*1 Whether TFL or TCC is read depends on the setting of the CTEST bit in the MSR
*2 Whether MDS or RST is read depends on the setting of the CTEST bit in the MSR
0
register.
register.
R/W Register Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
R
R
R
R
R
RDR
TDR
ENR
EIR
LSR
ICR1
ICR2
MSR
DSR
FCR
TFL (L)
TFL (H)
TCC (L)
TCC (H)
MDS (L)
MDS (H)
RST (L)
RST (H)
TEST
*1
*1
*1
*1
*2
*2
*2
*2
Receive data register
Transmit data register
Interrupt enable register
Interrupt event and status indication register
Status register
Transmit-receive control register
BOF count setting register
Register for setting a transfer mode and a data rate and selecting a
crystal to be used
DMA mode setting register
FIFO threshold setting register
Transmit frame-length setting register (low-order byte)
Transmit frame-length setting register (high-order byte)
Transmitter current-count register (low-order byte)
Transmitter current-count register (high-order byte)
Maximum data size setting register (low-order byte)
Maximum data size setting register (high-order byte)
Receiver frame length stack register (low-order byte)
Receiver frame length stack register (high-order byte)
Used for test.
Description
MSM9405
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