msm9405 Oki Semiconductor, msm9405 Datasheet
msm9405
Related parts for msm9405
msm9405 Summary of contents
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... Semiconductor MSM9405 IrDA Communication Controller GENERAL DESCRIPTION The MSM9405 is a communication controller conforming to IrDA, the international standard for infrared data communication. The device covers the IrDA physical specifications Ver.1.0 and 1.1. Since the device performs some of the functions concerning communication protocol control, the load on the software (firmware) for protocol control can be reduced ...
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... Semiconductor BLOCK DIAGRAM Microcontroller I/F MSM9405 2/30 ...
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... PIN CONFIGURATION (TOP VIEW XIN 30 XOUT 29 TEST 28 IRIN-A 27 IRIN-B 26 IROUT DREQ 22 DACK 21 PWDN 20 RESET 19 INTR GND 16 30-Pin Plastic SSOP MSM9405 3/30 ...
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... When set low, oscillation stops and the device enters power down (low supply current) mode. RESET System reset input. Active low. I When set low, the internal registers are initialized. TEST O Test. Must be left open. XIN I Crystal connect. XOUT O Crystal connect. V — Power supply. DD GND — Ground. MSM9405 Description * 4/30 ...
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... — — 0.4 O — — — 20 When PWDN = "L" — — — MSM9405 Rating Unit –0.5 to +4.0 V –0.5 to +6.0 V 230 mW –55 to +150 °C Unit V °C — = 2 –20 to +70°C) Unit Applicable Pin IRIN-A, IRIN-B, PWDN ...
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... Receiver 195 — t — 70 — rstw , the change from CS high to low, and the change from - the change from CS low to high, and the change from - MSM9405 Max. Unit Note — — ns — ns — ns — ...
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... Semiconductor • Read timing t rdd CS t rdd rdd INTR t rpw t t rpw t rpw t rdh t intr MSM9405 t rdh rdh t rcv 7/30 ...
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... Semiconductor • Write timing CS t was INTR t csh t css t wah t wpw t t wds MSM9405 t rcv wdh t intr 8/30 ...
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... DMA_EN = "1", DMA_SL = "0", DMA_SL 1 0 MemoryÆM9405 CS DREQ (Active low) DACK M9405ÆMemory CS DREQ (Active low) DACK "0" t drqr t dak t rpw t wds t drqr t dak t wpw t rdd MSM9405 t rcv t rcv t wdh t rcv t rdh t rcv t rdh 9/30 ...
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... DMA_SL 1 0 M9405ÆMemory DREQ t (Active high) DACK t acs MemoryÆM9405 DREQ (Active high) DACK t acs "1" drqr t rpw t rdd t drqr t wpw t wds t tcs MSM9405 t achr t rcv t rdh t achw t rcv t wdh t t tcw tch 10/30 ...
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... M9405ÆMemory DREQ t rdd MemoryÆM9405 DREQ "1" or "0" drqr t rpw t rdd t rpw t rpw t rdd t drqr t css t t was wah t wpw t wds MSM9405 t rdh t rdh t rdh t csh t wdh 11/30 ...
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... Semiconductor • Infrared interface timing t spw SIR t mpw MIR t fpw FIR • Reset timing RESET t rstw MSM9405 t fdpw 12/30 ...
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... ICR1 (Infrared Control Register 1). For sending, writing "1" in TX_EN puts the MSM9405 in the sending mode. Writing "1" in RX_EN puts the MSM9405 in the receiving mode. If "0" is written to both TX_EN and RX_EN bits, the MSM9405 does not perform sending/receiving but enters the idle state ...
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... Tout = 4 ¥ 8 ¥ 1/baud rate baud rate: Transfer rate (2.4 to 115.2 kbps) Register Map The MSM9405 contains 14 registers, of which 13 are available. Each register can be selected with the register address assigned from 0h through Ch. Various setting options are provided for each register to allow optimum communication. ...
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... RST RST RST RST RST MDS * * * * RST TEST TEST TEST TEST TEST MSM9405 Bit2 Bit1 Bit0 TDR TDR TDR /RDR /RDR /RDR FE_IE OE_IE CE_IE AS_IE ECE_IE * FE_EV OE_EV CE_EV AS_EV ECE_EV ...
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... ENR: Enable Register (Address = 1h) The ENR (Enable Register) is used to control enabling/disabling various interrupts on the MSM9405. Each of eight bits corresponds to each of eight interrupts provided on the MSM9405. Each of eight interrupts can be independently controlled by each bit. When the system is reset, all bits are reset to "0". By writing "1" to the bit corresponding to the desired interrupt, the specified interrupt is enabled ...
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... TXL_IE (Transmitter Low-Data-Level Interrupt Enable) : This bit enables/disables interrupt when the ENR[6] sent data is below the sending threshold level. TXE_IE (Transmitter Empty Interrupt Enable) : This bit enables/disables interrupt when both the ENR[7] FIFO and the TSR have become empty upon sending. Table bit MSM9405 17/30 ...
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... Semiconductor • EIR: Event Identification Register (Read Only) (Address = 2h) The EIR (Event Identification Register) indicates factors of various interrupts on the MSM9405. Each of eight bits corresponds to each interrupt bit assignment set on the ENR. The EIR works as the status register even if the interrupt is disabled. When an event occurs, each corresponding bit is set to " ...
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... TXE_EV (Transmitter Empty Event): When both FIFO and TSR are empty in sending mode, this bit EIR[7] is set to "1". When the CPU reads the EIR, this bit is set to "0". Description MSM9405 19/30 ...
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... Semiconductor • LSR: Line Status Register (Read Only) (Address = 3h) The LSR (Line Status Register) indicates various statuses of the MSM9405 that is running. When the system is reset, all bits of the LSR are set to "0". This register is for read only and cannot be written ...
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... Semiconductor • ICR1: Infrared Control Register 1 (Address = 4h) The ICR1 (Infrared Control Register 1) is used to set various environment so that the MSM9405 can perform IrDA communication under proper conditions. When the system is reset, all bits of ICR1 are set to "0". ICR1 ICR1 ...
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... TCC is enabled. When TCC_EN is set to "0", the TCC is disabled. To use S_EOT, the TFL must be set to the maximum value or the TCC must be disabled with TCC_EN = "0". MS_EN (Mode Select Enable): When "1" is written to this bit, the MSM9405 performs the following operation depending on the mode. After the operation is completed, this bit is automatically set to " ...
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... Semiconductor • ICR2: Infrared Control Register 2 (Address = 5h) The ICR2 (Infrared Control Register 2) is used to set various environment so that the MSM9405 can perform IrDA communication under proper conditions. When the system is reset, all bits of ICR2 are set to "0". ICR2 ICR2 ...
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... IRIN_SL = "1": An input from IRIN-A or IRIN-B is automatically selected depending on the transfer rate. (A: 2.4 to 115.2 kbps, B: 0.576 to 4 Mbps) SD_INV (SD Signal Invert): This bit changes the polarity (active high/low) of the SD pin output on the MSM9405. ICR2[6] SD_INV = "0": Active high ("H" output during shutdown) SD_INV = " ...
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... Semiconductor • MSR: Mode Select Register (Address = 6h) The MSR is used to select various modes of the MSM9405. When the system is reset, each bit is set to the initial value. MSR MSR MSR MSR MSR Bit IRSL (Infrared Mode Select): These bits are used to select the transfer mode as shown below. ...
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... Semiconductor • DSR: DMA Mode Select Register (Address = 7h) The DSR (DMA Mode Select Register) is used to select the DMA mode for the MSM9405. When the system is reset, all bits of DSR are set to "0". DSR DSR DSR DSR DSR Bit DMA_EN (DMA Mode Enable): This bit determines whether the DMA used. The initial value is set to " ...
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... FCR : FIFO Control Register (Address = 8h) The FCR (FIFO Control Register) is used to set the threshold level of the FIFO to be used by the MSM9405 upon sending/receiving. The FCR setting is applied to both interrupt and DMA. When the system is reset, the FCR is set to the initial value. ...
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... RST. This value is stored untill the next frame is fully received. The value stacked in the RST is maintained even if MSM9405 sending/receiving is switched. The RST initial value is set to 0h. TEST : Test Register (Address = Fh) This register is used for testing ...
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... Semiconductor APPLICATION CIRCUIT MSM9405 TC INTR DREQ DACK RESET PWDN IRIN-A RXD-A Infrared IRIN-B (RXD-B) Transceiver IROUT TXD Module SD SD XIN XOUT MSM9405 29/30 ...
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... Semiconductor PACKAGE OUTLINES AND DIMENSIONS Mirror finish 30-Pin Plastic SSOP MSM9405 (Unit : mm) 30/30 ...