ml7051la Oki Semiconductor, ml7051la Datasheet
ml7051la
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ml7051la Summary of contents
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... Bluetooth Baseband Controller IC GENERAL DESCRIPTION The ML7051LA is a CMOS digital IC for use in 2.4 GHz band Bluetooth systems. This IC incorporates the ARM7TDMI as the CPU core, features a highly expandable architecture, and supports the interfaces for a variety of applications. Used in conjunction with the ML7050LA (Bluetooth RF Transceiver IC) and the OKI Bluetooth Protocol Stack Software, data/voice communications are possible while maintaining interconnectivity with other Bluetooth systems ...
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... V ±0.3V, Vdd_core = 2.5 V ±10 70°C ) Symbol Conditions Min. Voh Ioh = –4 mA 2.4 Vol Iol = 4 mA — GND to 3.6 V – GND to Vdd –10 During 32 MHz Iddo 0 operation Idds CLK Stopped — FEDL7051LA-02 ML7051LA Rating Unit V V 1.35 W –55 to 150 °C Typ. Max. Unit 3.3 3.6 V 2.5 2.75 V — 3.6 V — 0.8 V — ...
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... MCSn0 MOEn0 CORE_ MA0 VDD GND ND7 MD0 VDD MD13 MD11 MD10 MD5 MD4 MD1 MD15 MD12 MD8 MD3 GND MWEn TOP VIEW FEDL7051LA-02 ML7051LA GND TDI REMAP1 RESETn VDD GND VDD TXC_IN RXD SCLK12 XCLK PUCTL VDD A_VDD DP VDD DM ...
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... Bluetooth transmit clock input (1 MHz) When the transmit clock is used by a clock L D13 (RXC) that is generated from the receive data, set TXCSEL(Pin# C11 and connect to RXC(Pin# C5). Bluetooth transmit clock setting pin L C11 L: Select 1 MHz divided by internal PLL. H: Select TXC_IN input signal. FEDL7051LA-02 ML7051LA 4/24 ...
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... MA11: J3; MA10: K1; MA9: L2; MA4: L3; MA3: N3; MA2: L4; MD13: M5; MD12: N6; MD11: M6; MD10: M7 MD7: L8; MD6: K8; MD5: M8; MD0: L10 FEDL7051LA-02 ML7051LA Description “01” Stacked Flash ROM “10” External MCS[1] device “11” External MCS[0] device Description MA8: K4; MA7: M2 MA1: M3; MA0: L5 MD4: M9; MD3: N8; 5/24 ...
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... Serial data input — E4 (Pin shared with GPIO6) Clock for serial data output, in the input state — E2 after initialization (Pin shared with GPIO5) Clock for serial data input, in the input state — F1 after initialization (Pin shared with GPIO4) FEDL7051LA-02 ML7051LA Description Description Description 6/24 ...
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... PCM data output — A3 PCM data input PCM sync signal (8 kHz), in the input state — A4 after initialization (can be switched by an internal register) PCM clock (64 kHz/128 kHz), in the input — C4 state after initialization (can be switched by an internal register) FEDL7051LA-02 ML7051LA Description Description Description Description 7/24 ...
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... Built-in Flash ROM test pin A1, A13 — No Connection N1, N13 Initial Pin Value Placement — [*5] I/O power pin 3.3 V ±0.3 V — [*6] Core power pin 2.5 V ±10% — [*7] Digital block ground pin — F13 Analog block power pin 2.5 V ±10% — E10 Analog block ground pin FEDL7051LA-02 ML7051LA Description Description 8/24 ...
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... Semiconductor BLOCK DIAGRAM SIO I/F Clock 16 ML7051LA FEDL7051LA-02 ML7051LA UART I/F SIO I/F PIO I/F USB I/F 9/24 ...
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... Synchronization detection (synchronizing within the permissable error limit of SyncWord) - Receive clock re-timing function FH Controller hopping - Sequence control - Frequency hopping selection function - CRC computation's initial value selection function Packet Composer Tx ACL Buffer FHCNT Security Timing Packet Decomposer FEDL7051LA-02 ML7051LA RF LSI TXD RF CNT CNT RXD 10/24 ...
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... Modem control based on CTS, DCD, and DSR Programmable serial interface 5-, 6-, 7-, 8-bit characters Generation and verification of odd parity, even parity parity 1, 1. stop bits Programmable Baud Rate Generator (1200 bps to 921.6 kbps) Error servicing for parity, overrun, and framing errors FEDL7051LA-02 ML7051LA 11/24 ...
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... PCMSYMC/PCMCLK I/O can be switched (in the input state after initialization) GPIO Block All 16 bits Input/Output selection possible for each bit Interrupts can be used for all 16 bits Interrupt masks and interrupt modes can be set for all bits In the input state immediately after a reset FEDL7051LA-02 ML7051LA 12/24 ...
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... TXCSEL = L : Use 1 MHz clock that was divided down from the internal PLL output (192 MHz). TXCSEL = H : Use external pin TXC_IN. Note: This clock can also be set by the CLKCNT register in the CTL/WDT block. HCI Transport Selection HCI is selected (USB/UART) according to the logical value of GPIO0 at initial powerup of ML7051LA. GPIO0 = L : UART is used as HCI. GPIO0 = H : USB is used as HCI ...
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... PCM format (data width of one PCM Linear sample) 8-bit (initial setting)/14-bit/16-bit - Serial interface format Short frame (initial setting)/long frame - Application interface mode PCM Codec I/F (initial setting)/APB I/F 3 GPIO0 1.5 k F11 PUCTL 16 G11 DP 16 G13 DM FEDL7051LA-02 ML7051LA D+ (3 (3.3 V) 14/24 ...
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... Semiconductor External Memory ML7051LA specifications for the devices that are connected to MCS[0] and MCS[1] are explained below. When connected to MCS[0] device memory bank - Bus width bits - Byte access control: BS/WE - Supported devices: Normal SRAM, Flash Memory, Page mode Flash memory Bus timing to MCS[0] device ...
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... Data OFF time clock cycles [*3] Address set-up time clock cycles [*4] Write data set-up time: 0 clock cycles (IOWRTYPE = clock cycles (IOWRTYPE=1) [*3] [*1] [*2] [*3] [*4] [*1] [*2] 1 clock fixed FEDL7051LA-02 ML7051LA [*1] 1 clock fixed [*1] 1 clock fixed n clock 16/24 ...
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... Connect MA0 to device A0 for devices that have an 8-bit data bus. - MOEn[0] is the AND signal for MCS[0] and MREn. Perform an open process when this is not in use. - MOEn[1] is the AND signal for MCS[1] and MREn. Perform an open process when this is not in use. FEDL7051LA-02 ML7051LA 17/24 ...
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... Open MBSn1 Open MOEn0 Open MOEn1 Open MWAIT Refer to GPIO1 FEDL7051LA-02 ML7051LA Comments Comments When connected For 16-bit devices: Open MA0. Connect from MA1 in order from A0 of the connected device. For 8-bit devices: Connect to each corresponding address. Only use when connecting to a device that has only one, but not both of CEn or REn ...
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... UART I/F Pin Name Process When Pin Not Used SOUT Refer to GPIO15 SIN Refer to GPIO14 DCD Refer to GPIO13 RTS Refer to GPIO12 CTS Refer to GPIO11 DSR Refer to GPIO10 DTR Refer to GPIO9 RI Refer to GPIO8 FEDL7051LA-02 ML7051LA Comments Pull up to Vdd when using USB. Comments 19/24 ...
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... Process When Pin Not Used TEST_L GND TEST_O Open SVCO0 Pull up to Vdd SVCO1 Pull down to GND VTM Open CLK GND NC Open When using UART: Pull down to GND — When using USB: Pull up to Vdd FEDL7051LA-02 ML7051LA Comments Comments Comments Comments Comments Comments 20/24 ...
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... FEDL7051LA-02 Comments 0: Do not use 1: Use Number of hopping channels 0: -law, 1: A-law, 2: Linear 0: 1200 bps 1: 2400 bps 2: 4800 bps 3: 7200 bps 4: 9600 bps 5: 19.2 kbps 6: 38.4 kbps 7: 56 kbps 8: 57.6 kbps 9: 115.2 kbps 9: 230.4 kbps 10: 345.6 kbps 11: 460.8 kbps 12: 921.6 kbps Unit: 625 sec ML7051LA 21/24 ...
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... At Oki Electric Industry Co., Ltd., we have made available the System Development Kit (SDK) for the following objectives: - Software development of the upper Bluetooth layer - Overall system software - Device development with embedded ML7050LA or ML7051LA Please contact Oki Electric Industry Co., Ltd. for more information regarding System Development Kit contents, pricing, etc. FEDL7051LA-02 ...
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... The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). FEDL7051LA-02 ML7051LA (Unit: mm) 23/24 ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. FEDL7051LA-02 ML7051LA Copyright 2000 Oki Electric Industry Co., Ltd. 24/24 ...