wm8400 Wolfson Microelectronics plc, wm8400 Datasheet - Page 109

• Manufacturer Part Number: wm8400
• Description: Wolfson Audioplustm Hi-fi Audio Codec And Power Management Unit For Mobile Multimedia
• Manufacturer: Wolfson Microelectronics plc

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Pre-Production
CODEC INTERRUPT EVENT OUTPUT
The CODEC interrupt status flag IRQ is asserted when any enabled CODEC interrupt event is
asserted. It represents the OR’d combination of all the enabled CODEC interrupt status bits. If
required, this flag may be inverted using the IRQ_INV register bit. The IRQ flag can be polled at any
time, or may be output directly on a GPIO pin. Configuration of the GPIO pins for output of the IRQ
flag is described in Table 63 and Table 64 and also in the example settings below.
An interrupt can be generated by any of the following events described earlier:
The CODEC interrupt events are indicated by the interrupt register fields described earlier. The
interrupt bits are latched once set; they are reset by writing a logic ‘1’ to the respective bit. Each of
these can be enabled as an input to the IRQ function by setting the associated _IRQ_ENA register
field. Note that the interrupt bits are always valid, regardless of the setting of the associated
_IRQ_ENA register fields.
The IRQ bit cannot be reset directly. This read-only bit is reset whenever none of the enabled
interrupts is set.
The interrupt behaviour is driven by level detection (not edge detection) of the enabled inputs.
Therefore, if an input remains asserted after the interrupt register has been reset, then the interrupt
status flag IRQ will be triggered again even though no transition has occurred. If edge detection is
required (eg. confirming that the input has been de-asserted), then the polarity inversion may be
used after each event in order to detect each rising and falling edge separately. This is described
further in the following “GPIO summary” section.
If direct output of the Interrupt signal is required to external pins of the WM8400, the following
register settings are required:
The IRQ Control fields are described in Table 68.
Note that the CODEC Interrupt relates only to the functions described in this section. The Power
Management Interrupt, and the dedicated NIRQ pin, are described separately in the “Interrupt
Events” section. The Jack Detect (GPI7 and GPI8), MICBIAS and Temperature sensor functions are
effective in both the CODEC Interrupt and Power Management Interrupt circuits.
Table 68 CODEC Interrupt (IRQ) Control
R18 (12h)
R23 (17h)
REGISTER
ADDRESS
•
•
•
•
•
•
•
•
•
•
•
•
Button Control input (on GPIO1 to GPIO6, GPI7 and GPI8)
MICBIAS current / short circuit / accessory detect
FLL Lock
Temperature Sensor
ALRCGPIO1 = 1 (only required if using GPIO1)
MCLK_SRC = 0 (only required if using GPIO2)
AIF_SEL = 0 (only required if using GPIO3, GPIO4 or GPIO5)
ALRCGPIO6 = 0 (only required if using GPIO6)
AIF_TRIS = 0
GPIOn_SEL = 0111 for the selected Interrupt (IRQ) output pin
GPIOn_PU = 0 for the selected Interrupt (IRQ) output pin
GPIOn_PD = 0 for the selected Interrupt (IRQ) output pin
12
12
BIT
IRQ
(ro)
IRQ_INV
LABEL
Read Only
0b
DEFAULT
IRQ Readback
(Allows polling of IRQ status)
IRQ Invert
0 = IRQ output active high
1 = IRQ output active low
DESCRIPTION
PP, April 2009, Rev 3.0
WM8400
109