wm8400 Wolfson Microelectronics plc, wm8400 Datasheet - Page 108

• Manufacturer Part Number: wm8400
• Description: Wolfson Audioplustm Hi-fi Audio Codec And Power Management Unit For Mobile Multimedia
• Manufacturer: Wolfson Microelectronics plc

WM8400
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Table 67 FLL Lock GPIO Control
LOGIC '1' AND LOGIC '0' OUTPUT
The GPIO pins can be programmed to drive a logic high or logic low signal. The following register
settings are required:
REGISTER
ADDRESS
R18 (12h)
R22 (16h)
R23 (17h)
•
•
•
•
•
•
•
•
•
ALRCGPIO1 = 1 (only required if using GPIO1)
MCLK_SRC = 0 (only required if using GPIO2)
AIF_SEL = 0 (only required if using GPIO3, GPIO4 or GPIO5)
ALRCGPIO6 = 0 (only required if using GPIO6)
AIF_TRIS = 0
GPIOn_SEL = 0010 for each Logic ‘0’ output pin
GPIOn_SEL = 0011 for each Logic ‘1’ output pin
GPIOn_PU = 0 for each Logic ‘0’ or Logic ‘1’ GPIO pin
GPIOn_PD = 0 for each Logic ‘0’ or Logic ‘1’ GPIO pin
8
8
8
BIT
FLL_LCK
(rr)
FLL_LCK_IRQ_
ENA
FLL_LCK_POL
LABEL
0b
0b
0b
DEFAULT
FLL Lock CODEC interrupt
0 = interrupt not set
1 = interrupt is set
This bit is latched once set. The
FLL_LCK_POL bit determines the polarity of
the input event to set this bit. It is cleared
when a ‘1’ is written.
FLL Lock CODEC IRQ Enable
0 = disabled
1 = enabled
FLL Lock polarity
0 = Non-inverted
1 = Inverted
DESCRIPTION
PP, April 2009, Rev 3.0
Pre-Production
108