ak4141 AKM Semiconductor, Inc., ak4141 Datasheet - Page 17

• Manufacturer Part Number: ak4141
• Description: Nicam/a2/eia-j Digital Stereo Decoder
• Manufacturer: AKM Semiconductor, Inc.

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The external clocks, which are required to operate the AK4141, are MCLK(or XTI), LRCK and SCLK. The MCLK(or
XTI) should always be present whenever the AK4141 is in normal operation, and should be synchronized with LRCK but
the phase is not critical. The on-chip X’tal oscillator or external system clock through MCKI can be used for the AK4141
operation. If the external clocks are not present, the AK4141 should be in the power-down mode (PDN pin = “L”) or in
the reset mode (RSTN bit = “0”). After exiting reset at power-up etc., the AK4141 is in the power-down mode until
MCLK(or XTI) and LRCK are input.
The AK4141 supports both master mode (SCLK, LRCK = output) and slave mode (SCLK, LRCK = input). The AK4141
is master mode when MSN pin = “H”, slave mode when MSN pin = “L”. SRC inputs (SCLK4/5, LRCK4/5) are always
slave mode (input) and can operate asynchronously.
The MSN pin and the CKS2-0 bits select the clock frequency
always be supplied except in the power-down mode. The AK4141 is in power-down mode until the clock is supplied.
MS0952-E-00
MSN pin
System Clock
H
H
L
L
L
L
L
L
L
L
32.0kHz
44.1kHz
48.0kHz
LRCK
CKS2 bit
fs
0
0
0
0
1
1
1
1
0
1
PDN pin
H
L
4.0960
5.6448
6.1440
128fs
CKS1 bit
0
0
1
1
0
0
1
1
x
x
MSN pin
6.1440
7.5264
9.2160
192fs
CKS0 bit
H
H
L
L
0
1
0
1
0
1
0
1
x
x
Table 3. System clock example
OPERATION OVERVIEW
Table 2. System clock control
Table 1. Master/Salve Mode
11.2896
12.2880
8.1920
256fs
Output “L” (master mode)
Output (master mode)
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
/Slave
Slave
Input (slave mode)
Input (slave mode)
SCLK, LRCK
- 17 -
MCLK (MHz)
(Table
12.2880
16.9344
18.4320
384fs
128fs, 192fs, 256fs, 384fs, 512fs, 768fs, 1024fs
128fs
192fs
256fs
384fs
512fs
768fs
1024fs
256fs
1024fs
note: when CKS2-0 bits are default.
2). The external clock (X’tal or MCKI) should
16.3840
22.5792
24.5760
512fs
SCLK4/5, LRCK4/5
Master Clock Speed
Input (slave mode)
Input (slave mode)
Input (slave mode)
Input (slave mode)
24.5760
33.8688
36.8640
768fs
(register default)
(register default)
32.7680
45.1584
49.1520
1024fs
(x: Don’t care.)
[AK4141]
2008/05