ak4620b AKM Semiconductor, Inc., ak4620b Datasheet
ak4620b
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ak4620b Summary of contents
Page 1
... ASAHI KASEI The AK4620B is a high performance 24-bit CODEC that supports up to 192kHz record and playback. The on-board analog-to-digital converter has a high dynamic range due to AKM’s Enhanced Dual-Bit architecture. The DAC utilizes AKM’s Advanced Multi-Bit architecture that achieves low out-of-band noise and high jitter tolerance through the use of Switched Capacitor Filter (SCF) technology ...
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... DGND DATT PDN LRCK BICK Audio I/F SDTO Controller SDTI MCLK DFS0 Control Register I/F P/S CSN/ CCLK/ CDTI/ DIF CKS1 CKS0 AK4620B 216kHz Single-ended Differential 0 ~ +18dB - 0.5dB/step Mute,-63.5dB ~ 0dB 0.5dB/step 0.5dB/step 90dB 100dB 110dB 113dB 100dB X 97dB 115dB Mute, -48dB ~ 0dB Linear 256 steps ...
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... AINL+ 4 AINL-/NC 5 VREF 6 AGND P MCLK 11 LRCK/DSDR BICK/DCLK 12 13 SDTO SDTI/DSDL 14 OVFR/DZFR 15 MS0401-E-00 30pin VSOP (0.65mm pitch) AOUTR+ 30 AOUTR AOUTL+ AOUTL- 27 DGND Top View ADMODE 22 DEM0 PDN 21 20 DFS0 19 CSN/DIF CCLK/CKS1 18 17 CDTI/CKS0 16 OVFL/DZFL - 3 - [AK4620B] 2005/07 ...
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... Power down reset and initialize the control register, “H”: Power up 22 DEM0 I De-emphasis Control Pin Analog Input Mode Select Pin 23 ADMODE I “L”: Single-ended Input & IPGA Enable “H”: Differential Input & IPGA Bypass MS0401-E-00 PIN/FUNCTION 2 S compatible - 4 - [AK4620B] 2005/07 ...
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... These pins should be open when ADMODE pin = “L”. AINL+ pin is connected to AINL-/NC pin when ADMODE pin = “H”. AINR+ pin is connected to AINR-/NC pin when ADMODE pin = “H”. These pins should be open. This pin should be connected to DVSS. These pins should be open [AK4620B] Setting 2005/07 ...
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... MS0401-E-00 ABSOLUTE MAXIMUM RATINGS Symbol min VA -0.3 VD -0.3 VT -0.3 ∆GND (Note 2) - IIN - (Note 3) VINA -0.3 (Note 4) VIND -0.3 Ta -10 Tstg -65 Symbol min VA 4. VREF 3 [AK4620B] max Units 6.0 V 6.0 V 6.0 V 0.3 V ±10 mA VA+0.3 V VT+0.3 V °C 70 °C 150 typ max Units 5.0 5.25 V 3.3 3.6 V 5.0 5. 2005/07 ...
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... Note 100 - 50 - 100 - 46 - 100 - 46 - 113 103 113 90 120 0.1 20 (Note [AK4620B] max Units 3.37 Vpp - kΩ 0 Bits 0 ppm/°C dB max Units 24 Bits ±3.02 Vpp - kΩ - kΩ - kΩ - kΩ ...
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... Units 24 Bits 0 ppm/°C ±3.0 Vpp 25 pF kΩ max Units ...
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... SB 53 100 GD 43.1 ∆ 2.0 13.0 Symbol min typ 88.18 - 89.0 - 96.0 SB 106 100 GD 38.2 ∆ 4.0 26 [AK4620B] max Units 19.8 kHz - kHz - kHz - kHz kHz ±0.005 dB dB 1/fs µ max Units 43.0 kHz - kHz - kHz - kHz kHz ±0.005 dB dB 1/fs µ max Units 86.0 kHz ...
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... Symbol min typ 48 ± 0.3 - symbol min typ 96.0 SB 105 +0/- [AK4620B] max Units 20.0 kHz - kHz kHz ± 0.005 1/ max Units 43.5 kHz - kHz kHz ± 0.005 1/ max Units 87.0 kHz - kHz kHz ± 0.005 ...
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... Symbol min typ 39 +0/-4 Symbol min typ 79.1 SB 171 +0/- [AK4620B] max Units 8.1 kHz - kHz kHz ± 0.005 1/ max Units 17.7 kHz - kHz kHz ± 0.005 1/ max Units 35.5 kHz - kHz kHz ± 0.005 dB dB ...
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... Pulse Width High DCLK Edge to DSDL/R (Note 24) Note 22. When the normal/double/quad speed modes are switched, the AK4620B should be reset by PDN pin or RSTN bit. Note 23. BICK rising edge must not occur at the same time as LRCK edge. Note 24. DSD data transmitting device must meet this time. ...
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... CCLK “↑” to CSN “↑” Reset Timing PDN Pulse Width (Note 25) RSTAD “↑” to SDTO valid (Note 26) Note 25. The AK4620B can be reset by bringing PDN pin “L”. Note 26. These cycles are the number of LRCK rising from RSTAD bit. MS0401-E-00 Symbol min typ ...
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... MCLK tCLKH LRCK BICK tBCKH LRCK tBLR BICK tLRS SDTO SDTI MS0401-E-00 1/fCLK tCLKL 1/fs tBCK tBCKL Clock Timing tLRB tSDS tSDH Audio Interface Timing (PCM mode [AK4620B] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tBSD 50%VD VIH VIL 2005/07 ...
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... Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”) DCLK tDDD DSDL DSDR Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”) MS0401-E-00 tDCK tDCKL tDCKH tDCK tDCKL tDCKH tDDD - 15 - [AK4620B] VIH VIL VIH VIL VIH VIL VIH VIL 2005/07 ...
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... CSN CCLK CDTI D3 PDN MS0401-E-00 tCCKL tCCKH tCDS tCDH C0 R/W WRITE Command Input Timing WRITE Data Input Timing tPD Power Down & Reset Timing - 16 - [AK4620B] VIH VIL VIH VIL VIH A4 VIL tCSW VIH VIL tCSH VIH VIL VIH VIL VIL 2005/07 ...
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... AK4620B may draw excess current due to dynamic refresh of internal logic. If the external clocks are not present, the AK4620B should be in the power-down mode (PDN pin = “L” or power down both the ADC and DAC by the register). After exiting reset (PDN pin = “L” ...
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... L 256fs H 512fs L 384fs Auto Setting Mode (*) H 1024fs Mode Normal speed Double speed Quad speed - 18 - [AK4620B] MCLK Quad Speed (DFS1-0 = “10”) N/A Default 128fs 256fs N/A N/A 192fs Sampling Rate 32kHz-54kHz 54kHz-108kHz 108kHz-216kHz MCLK Double Speed ...
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... The AK4620B should be reset by PDN pin = “L” after these clocks are provided. If the external clocks are not present, the AK4620B should be in the power-down mode (PDN pin = “L”). After exiting reset (PDN pin = “↑”) at power-up etc., the AK4620B is in the power-down mode until MCLK is provided. ...
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... Figure 4. Mode 2 Timing Don’t Care 23 22 Lch Data Figure 5. Mode 3 Timing - 20 - [AK4620B Rch Data ...
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... BICK(64fs) SDTO( SDTI(i) Don’t Care 23 22 23:MSB, 0:LSB Lch Data MS0401-E- Don’t Care Figure 6. Mode 4 Timing - 21 - [AK4620B Rch Data 2005/07 ...
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... Caution: In DSD mode, the signal level ranges from 25% to 75%. Peak levels of DSD signal above this range are not recommended by the SACD format book (Scarlet Book). MS0401-E- Figure 7. DSD Mode Timing ≥4/fs PCM Mode DSD Mode ≥4/fs DSD Data - 22 - [AK4620B DSD Mode ≥0 DSD Data PCM Mode PCM Data 2005/07 ...
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... Output Volume The AK4620B includes channel independent digital output volumes (ATT) with 256 levels at linear steps including MUTE. These volumes are in front of the DAC and can attenuate the input data from 0dB to −48dB and mute. When changing levels, transitions are executed via soft changes, eliminating any switching noise. The transition time of 1 level and all 256 levels is shown in Table 13 ...
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... DEM1 bit is fixed to “0” and only the DEM0 pin can be controlled (44.1kHz or OFF). When in DSD mode, DEM1-0 bits are ignored. The setting value is held even if PCM mode and DSD mode are switched Table 14. De-emphasis control (Normal Speed Mode) MS0401-E-00 DEM1 DEM0 Mode 0 0 44.1kHz 0 1 OFF 1 0 48kHz 1 1 32kHz - 24 - [AK4620B] Default 2005/07 ...
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... DZF pin immediately goes to “L” if input data are not zero after going DZF pin “H”. MS0401-E-00 Lch L Single-ended Single-ended H Differential Differential AMR bit Lch 0 0 Single-ended 0 1 Single-ended 1 0 Differential 1 1 Differential X X Differential ( (2) (4) 8192/fs Figure 10. Soft Mute and Zero Detection - 25 - [AK4620B] Rch Rch Single-ended Differential Single-ended Differential Differential (1) ( (2) 2005/07 ...
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... Power Down & Reset The ADC and DAC of AK4620B are placed in power-down mode by bringing the PDN pin = “L”. Each digital filter is also reset at the same time. The internal register values are initialized by bringing PDN pin to “L”. This reset should always be done after power-up. As both control registers of the ADC and the DAC go to the reset state (RSTAD bit = RSTDA bit = “ ...
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... Some pop noise may occur at “*”. Figure 12. Reset & Power Down Sequence in parallel mode MS0401-E-00 Normal 80H “0” FI Output Normal Output MCLK, LRCK, BICK The clocks can be stopped [AK4620B] PD INITA Normal 00H 00H 80H 80H “0” FI Output PD Normal Hi-Z ...
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... Chip A ddress (Fixed to “10”) READ/WRITE (Fixed to “1”:WRITE) Register Address Cont rol data Figure 13. Control I/F Timing - 28 - [AK4620B] Serial mode 2005/07 ...
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... Control Register Setup Sequence When the PDN pin goes “L” to “H” upon power-up etc., the AK4620B will be ready for normal operation by the next sequence. In this case, all control registers are set to default values and the AK4620B is in the reset state. ...
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... DZF goes “H” at Zero Detection (Default) 1: DZF goes “L” at Zero Detection SLOW: DAC Slow Roll-off Filter Enable 0: Sharp Roll-off Filter (Default) 1: Slow Roll-off Filter MS0401-E- DZFB ZOE ZOS [AK4620B PWVR PWAD PWDA 2005/07 ...
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... Default: 24bit MSB justified for both ADC and DAC MS0401-E- D/P DCKS DCKB DIF2 DIF1 DIF0 CMODE [AK4620B AML AMR RSTAD RSTDA CKS1 CKS0 DFS1 DFS0 2005/07 ...
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... Disable SMUTE: DAC Input Soft Mute control 0: Normal operation (Default) 1: DAC outputs soft-muted The soft mute is independent of the output ATT and performed digitally. MS0401-E- ZCEI HPRN HPLN [AK4620B ZTM1 ZTM0 DEM1 DEM0 2005/07 ...
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... Refer to Table 10 Default: 80H (0dB) The AK4620B includes two channel-independent analog volumes (IPGA), each with 32 levels in 0.5dB increments. These are located in front of the ADC while digital volume controls (IATT) with 128 levels (including MUTE) are located after the ADC. Control of both of these volume settings is handled by the same register address (04H for L-ch, 05H for R-ch). When the MSB of the register is “ ...
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... AINL- DGND VREF VD AK4620B AGND VT VA ADMODE P/S DEM0 PDN MCLK LRCK DFS0 BICK CSN/DIF SDTO CCLK/CKS1 SDTI CDTI/CKS0 OVFR/DZFR OVFL/DZFL - 34 - [AK4620B] 30 Rch Rch Out LPF 29 28 Lch Lch Out LPF 27 26 3.0 ∼ 3.6V 25 Digital Supply 0.1u 0.1u 3.0 ∼ 5.25V 24 Digital Supply Mode ...
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... AOUTL- NC DGND VREF VD AK4620B AGND VT VA ADMODE P/S DEM0 MCLK PDN LRCK DFS0 BICK CSN/DIF SDTO CCLK/CKS1 SDTI CDTI/CKS0 OVFR/DZFR OVFL/DZFL - 35 - [AK4620B] 30 Rch Rch Out LPF 29 28 Lch Lch Out LPF 27 26 3.0 ∼ 3.6V 25 Digital Supply 0.1u 0.1u 3.0 ∼ 5.25V 24 Digital Supply Mode ...
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... ADC Output The ADC output data format is 2’s complement. The DC offset, including the ADC’s own DC offset, is removed by the internal HPF. The AK4620B samples the analog inputs at 128fs. The digital filter rejects noise above the stopband except for multiples of 128fs. ...
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... Full-Differential Input (ADMODE pin = “H”) The AK4620B can accept input voltages from AGND to VA. The input signal range scales with the VREF voltage and is nominally 2.82Vpp (VREF = 5V), centered around the internal common voltage (about VA/2). Figure 17 shows an input buffer circuit example. This is a fully differential input buffer circuit with an inverted amplifier (gain: − ...
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... Figure 18. External LPF Circuit Example 1 for PCM (fc = 136kHz, Q=0.694) Table 18. Filter Response of External LPF Circuit Example 1 for PCM MS0401-E-00 4.7k 4.7k 200 330p +Vop 2.2n 200 4.7k -Vop 4.7k 330p Frequency Response Gain −0.01dB 20kHz −0.06dB 40kHz −0.59dB 80kHz - 38 - [AK4620B] Analog Out 2005/07 ...
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... Table 19. Filter Response of External LPF Circuit Example 2 for PCM MS0401-E-00 + 10u 0.1u 10u + 0.1u + 10u 0.1u 10u + 0. Stage 2 Stage 182kHz 284kHz 0.637 - +3.9dB -0.88dB 20kHz -0.025 -0.021 40kHz -0.106 -0.085 80kHz -0.517 -0.331 - 39 - [AK4620B] +15 -15 10u 0.1u 560 + 1.0n 100 620 Lch + 3 7 620 1.0n NJM5534D + 0.1u 10u Total - - +3.02dB -0.046dB -0.191dB -0.848dB 2005/07 ...
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... It is recommended by SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass filter with a cut-off frequency of maximum 50kHz and a slope of minimum 30dB/Oct. The AK4620B can achieve this filter response by combination of the internal filter (Table 20) and an external filter (Figure 20). ...
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... VSOP (Unit: mm) *9.7±0.1 0 0.22±0.1 0.12 M NOTE: Dimension "*" does not include mold flash. Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Solder (Pb Free) plate MS0401-E-00 PACKAGE 16 15 0.65 Detail A 0.08 Epoxy [AK4620B] 1.5MAX A +0.10 0.15 -0.05 2005/07 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0401-E-00 MARKING AKM AK4620BVF XXXBYYYYC XXXBYYYYC Date code identifier Revision History Reason Page Contents First Edition IMPORTANT NOTICE - 42 - [AK4620B] 2005/07 ...