ep1m120 Altera Corporation, ep1m120 Datasheet - Page 64

• Manufacturer Part Number: ep1m120
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Mercury Programmable Logic Device Family Data Sheet
SignalTap
Embedded
Logic Analyzer
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
64
Lock Signals
The Mercury device general purpose PLL circuits support individual
LOCK signals. The LOCK signal drives high when the PLL has locked onto
the input clock. Lock remains high as long as the input remains within
specification. It will go low if the input is out of specification. A LOCK pin
is optional for each PLL used in the Mercury devices; when not used, they
are I/O pins. This signal is not available internally; if it is used in the core,
it must be fed back in with an input pin.
Mercury devices include device enhancements to support the SignalTap
embedded logic analyzer. By including this circuitry, the Mercury device
provides the ability to monitor design operation over a period of time
through the IEEE Std. 1149.1 JTAG circuitry; a designer can analyze
internal logic at speed without bringing internal signals to the I/O pins.
This feature is particularly important for advanced packages such as
FineLine BGA packages, because it can be difficult to add a connection to
a pin during the debugging process after a board is designed and
manufactured.
All Mercury devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be
performed before or after configuration, but not during configuration.
Mercury devices can also use the JTAG port for configuration with the
Quartus II software or with hardware using either Jam Standard Test and
Programming Language (STAPL) Files (.jam) or Jam STAPL Byte-Code
Files (.jbc). Mercury devices also use the JTAG port to monitor the logic
operation of the device with the SignalTap embedded logic analyzer.
Mercury devices support the JTAG instructions shown in
Altera Corporation
Table
16.