ep1m120 Altera Corporation, ep1m120 Datasheet - Page 63

• Manufacturer Part Number: ep1m120
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
Advanced ClockShift Circuitry
General purpose PLLs in Mercury devices have advanced ClockShift
circuitry that provides programmable phase shift and fine tune time delay
shift. For phase shifting, users can enter a phase shift (in degrees or time
units) that affects all PLL outputs. Phase shifts of 90, 180, and 270 can be
implemented exactly. Other values of phase shifting, or delay shifting in
time units, are allowed with a resolution range of 0.3 ns to 1.0 ns. This
resolution varies with frequency input and the user-entered
multiplication and division factors. The phase shift ability is only possible
on a multiplied or divided clock if the input and output frequency have
an integer multiple relationship (i.e., f
integer).
In addition to the phase shift feature that affects all outputs, there is an
advanced fine time delay shift control on each of the four PLL outputs.
Each PLL output can be shifted in 250-ps increments for a range of –2.0 ns
to +2.0 ns. This ability can be used in conjunction with the phase shifting
ability that affects all outputs. f
relationship for the advanced fine time delay shift control.
Clock Enable Signal
Mercury PLLs have a CLKLK_ENA pin for enabling/disabling all of the
device PLLs. When the CLKLK_ENA pin is high, the PLL drives a clock to
all its output ports. When the CLKLK_ENA pin is low, the clock0,
clock1, clock2 and extclock ports are driven by GND and all of the
PLLs go out of lock. When the CLKLK_ENA pin goes high again, the PLL
must relock.
The individual enable port for each general purpose PLL is
programmable. If more than one general-purpose PLL is instantiated,
each one does not have to use the clock enable. To enable/disable the
device PLLs with the CLKLK_ENA pin, the inclocken port on the
altclklock instance must be connected to the CLKLK_ENA input pin.
Normal Mode: The external clock output pin will have phase delay
relative to the clock input pin. If an internal clock is used in this mode,
the IOE register clock will be phase aligned to the input clock pin.
Multiplication is allowed with the normal mode.
Mercury Programmable Logic Device Family Data Sheet
IN
/f
OUT
IN
does not need to have an integer
/f
OUT
or f
OUT
/f
IN
must be an
TM
63
13