cyrf6936 Cypress Semiconductor Corporation., cyrf6936 Datasheet - Page 25

• Manufacturer Part Number: cyrf6936
• Description: Wirelessusb Lp 2.4 Ghz Radio Soc
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-16015 Rev. *G
Mnemonic
Bit
Default
Read/Write
Function
Bits 7:4
Bits 3:0
Mnemonic
Bit
Default
Read/Write
Function
Bits 7:6
Bit 5
Bits 4:3
Bits 2:1
Bit 0
Mnemonic
Bit
Default
Read/Write
Function
This register provides the ability to override some automatic features of the device.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Not Used.
The most significant 4 bits of the synthesizer trim value. Typically, this register is loaded with 0x05 during initialization.
Reserved. Must be zero.
Manually Initiate Synthesizer. Setting this bit forces the synthesizer to start. Clearing this bit has no effect. For this bit to operate
correctly, the oscillator must be running before this bit is set.
Force Awake. Force the device out of sleep mode. Setting both bits of this field forces the oscillator to keep running at all times
regardless of the END STATE setting. Clearing both of these bits disables this function.
Not Used.
Reset. Setting this bit forces a full reset of the device. Clearing this bit has no effect.
When this bit is set, the device uses the transmit synthesizer frequency rather than the receive synthesizer frequency for the
given channel when automatically entering receive mode.
When this bit is set and ACK EN is enabled, the transmission of the ACK packet is delayed by 20 μs.
Force Expected Packet Type. When this bit is set, and the device is in receive mode, the device is configured to receive an
ACK packet at the data rate defined in TX_CFG_ADR.
Force Receive Data Rate. When this bit is set, the receiver ignores the data rate encoded in the SOP symbol, and receives
data at the data rate defined in TX_CFG_ADR.
Reject packets with a zero-seed CRC16. Setting this bit causes the receiver to reject packets with a zero-seed, and accept only
packets with a CRC16 that matches the seed in CRC_SEED_LSB_ADR and CRC_SEED_MSB_ADR.
The RX CRC16 checker is disabled. If packets with CRC16 enabled are received, the CRC16 is treated as payload data and
stored in the receive buffer.
Accept Bad CRC16. Setting this bit causes the receiver to accept packets with a CRC16 that do not match the seed in
CRC_SEED_LSB_ADR and CRC_SEED_MSB_ADR. An ACK is to be sent regardless of the condition of the received CRC16.
Not Used.
Not Used
ACK RX
RSVD
R/W
W
7
7
0
7
0
-
-
RXTX DLY
Not Used
MODE_OVERRIDE_ADR
RSVD
TX_OFFSET_MSB_ADR
R/W
W
6
6
0
6
0
-
-
RX_OVERRIDE_ADR
MAN RXACK
FRC SEN
Not Used
R/W
W
5
5
0
5
0
-
-
FRC RXDR
Not Used
R/W
W
4
4
0
4
0
-
-
FRC AWAKE
DIS CRC0
R/W
R/W
W
3
0
3
0
3
0
DIS RXCRC
Not Used
R/W
R/W
2
0
2
2
0
-
-
STRIM MSB
Not Used
ACE
Address
R/W
Address
Address
R/W
1
0
1
1
0
-
-
CYRF6936
Page 25 of 40
Not Used
R/W
RST
W
0
0
0
0
0
-
-
0x1C
0x1D
0x1E
[+] Feedback