cyrf6936 Cypress Semiconductor Corporation., cyrf6936 Datasheet - Page 17

• Manufacturer Part Number: cyrf6936
• Description: Wirelessusb Lp 2.4 Ghz Radio Soc
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-16015 Rev. *G
Mnemonic
Bit
Default
Read/Write
Function
The state of all IRQ Status bits is valid regardless of whether or not the IRQ is enabled. The IRQ output of the device is in its active state
whenever one or more bits in this register is set and the corresponding IRQ enable bit is also set. Status bits are non-atomic (different flags
may change value at different times in response to a single event).
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Receive Overwrite Interrupt Status. This IRQ is triggered when the receive buffer is overwritten by a packet being received
before the previous packet has been read from the buffer. This bit is cleared by writing any value to this register. This condition
is only possible when the RXOW EN bit in RX_CFG_ADR is set. This bit must be written ‘1’ by firmware before the new packet
may be read from the receive buffer.
Start of packet detect. This bit is set whenever the start of packet symbol is detected.
Receive Buffer Full Interrupt Status. This bit is set whenever the receive buffer is full, and cleared otherwise.
Receive Buffer Half Full Interrupt Status. This bit is set whenever there are eight or more bytes remaining in the receive buffer.
Firmware must read exactly eight bytes when reading RXB8 IRQ.
Receive Buffer Not Empty Interrupt Status. This bit is set any time that there are one or more bytes in the receive buffer, and
cleared when the receive buffer is empty. It is possible, in rare cases, that the last byte of a packet may remain in the buffer
even though the RXB1 IRQ flag has cleared. This can ONLY happen on the last byte of a packet and only if the packet data is
being read out of the buffer while the packet is still being received. The flag is trustworthy under all other conditions, and for all
bytes prior to the last. When using RXB1 IRQ and unloading the packet data during reception, the user must make sure the
RX_COUNT_ADR value, after the RXC IRQ/RXE IRQ, is set and unload the last remaining bytes if the number of bytes
unloaded is less than the reported count, even though the RXB1 IRQ is not set.
Receive Buffer Error Interrupt Status. This IRQ is triggered in one of two ways: (1) When the receive buffer is empty and there
is an attempt to read data (2) When the receive buffer is full and more data is received; this flag is cleared when RX GO is set
and a SOP is received.
Packet Receive Complete Interrupt Status. This IRQ is triggered when a packet has been received. If transaction mode is
enabled, then this bit is not set until after transmission of the ACK. If transaction mode is not enabled then this bit is set as soon
as a valid packet is received. This bit is cleared when this register is read. RXC IRQ and RXE IRQ flags may change value at
different times in response to a single event. There are cases when this bit is not triggered when ACK EN = 1 and there is an
error in reception. Therefore, firmware should examine RXC IRQ, RXE IRQ, and CRC 0 to determine receive status. If the first
read of this register returns RXC IRQ = 1 and RXE IRQ = 0 then firmware must execute a second read to this register to deter-
mine if an error occurred by examining the status of RXE IRQ. If the first read of this register returns RXC IRQ = 1 and
RXE IRQ = 1, then the firmware must not execute a second read to this register for a given transaction.
Receive Error Interrupt Status. This IRQ is triggered when there is an error in reception. It is triggered whenever a packet is
received with a bad CRC16, an unexpected EOP is detected, a packet type (data or ACK) mismatch, or a packet is dropped
because the receive buffer is still not empty when the next packet starts. The exact cause of the error may be determined by
reading RX_STATUS_ADR. This bit is cleared when this register is read.
RXOW IRQ
R/W
7
-
SOPDET IRQ
RX_IRQ_STATUS_ADR
R
6
-
RXB16 IRQ
R
5
-
RXB8 IRQ
R
4
-
RXB1 IRQ
R
3
-
RXBERR IRQ
R
2
-
RXC IRQ
Address
R
1
-
CYRF6936
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RXE IRQ
R
0
-
0x07
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