hsp50215 Intersil Corporation, hsp50215 Datasheet - Page 8

• Manufacturer Part Number: hsp50215
• Description: Digital Upconverter
• Manufacturer: Intersil Corporation

TABLE 2. EXAMPLES OF THE DIFFERENT CASES AND
Shaping Filter Application Issues
Note that when using quadrature modulation,
saturation/overflow can occur when the input values for I and Q
exceed 0.707 peak. Also note that there is gain in Interpolation
filter. Because of these two implementation constraints, the
Shaping filter coefficients may need to be reduced from full
scale to provide unity gain in the PUC and to prevent saturation
in the shaping filter. After the shaping filter computation, a gain
scaling control is provided. It is possible to allow the shaping
filter computation to approach unity on each channel and then
scale the I/Q magnitudes in the Gain Control.
The delay through the shaping and interpolation filters is 20
CLKs and the shaping filter delay.
Gain Control
Between the Shaping filter and the Interpolation filter is a gain
adjustment stage that provides for identical scaling of the I
and Q shaped signals. Gain adjustment is from 0 to slightly
less than unity. This gain control can be used to prevent signal
overflow in the Interpolation filter or saturation in the
quadrature mixer.
The interpolation filter can have a gain of 2dB. If a full scale
signal is required at the output of the shaping filter, apply 2dB
back off in the Gain Adjust Circuit. For worst case conditions,
the interpolation filter can have 25% overshoot. (See the
annotations on the Functional Block Diagram). Gain control
can also be used to set the level of a signal prior to summing
multiple signals in the Modulated Output Section.
The scaling multiplier value is programmed using an bits 0-7
in Control Word 17. The attenuation is set by:
Gain = OutGain/2
Gain
OutGain =
OutGain
(f
EXAMPLE
CLK
dB
1
2
3
4
5
6
= 48MHz for industrial temperature range).
=
=
DIFFERENT FIR INPUT SAMPLING FREQUENCIES
20
Gain 2
10
log
52MHz
52MHz
52MHz
52MHz
52MHz
52MHz
Gain
f
CLK
8
OutGain 2
8
dB
Hex
20
3-429
2
DS
16
16
16
10
8
4
8
8
Hex
16
IP
8
4
4
4
4
52/256 = 203kHz
52/128 = 406kHz
52/64 = 813kHz
52/40 = 1300kHz
52/32 = 1625kHz
52/16 = 3,250kHz
MAX f
S
(EQ. 5C)
(EQ. 5A)
(EQ. 5B)
(EQ. 5)
HSP50215
where Gain is the desired signal level relative to fullscale,
Gain
and OutGain is the control word value.
Table 3 details a few key control words and the associated
attenuations for the I and Q signals.
Re-Sampling NCO
The Sample Rate NCO provides the sample clock and
sample clock phase information to both the shaping and
Interpolation filters. Figure 8 details the conceptual design.
The sample frequency is set with 30-bit resolution. The LSB is
REFCLK/2
The MSB of the accumulator is the sample clock for the filters.
Four bits of coarse timing phase resolution control the
Shaping filter, while twelve bits of fine timing phase resolution
control the Interpolation filter.
The Resampling NCO frequency control word is double
buffered. The 30-bit timing NCO frequency is written to
Control Addresses 2 and 3. The frequency control word is
transferred from the buffer into the Re-Sampling NCO on a
pulse from SYNCIN or on a write to Control Word 2. Control
Word 22, bit 0, sets which action, (the SYNCIN or write to
CW2), causes a frequency control word transfer in the NCO.
Assertion of RST stops the Re-Sampling NCO and clears
the accumulator contents. It is held disabled until a SYNCIN
or write to Control Word 3 generates an EnNCO signal to
restart the NCO.
The PUC input sample rate is set by the Re-Sampling NCO.
The maximum error is 52MHz/(2
commercial part and 48MHz/(2
industrial part. The frequency control word is computed by:
F
where SR(29:0) is the 30-bit frequency control word and
f
Equation 6 can be rearranged to solve for SR(29:0).
SR(29:0) = RND
The range of SR(29:0) is: [0 to 2
CLK
RESAMP
CONTROL WORD
dB
1111 1111yt
is REFCLK.
1000 0000
0100 0000
0010 0000
0001 0000
0000 1000
0000 0100
0000 0010
0000 0001
is the desired signal level in dB relative to fullscale,
=
TABLE 3. SCALING GAIN ATTENUATION
32
SR 29:0
. The internal accumulator resolution in 32 bits.
f
------------------------- -
RESAMP
f
CLK
f
CLK
-12.041
-18.062
-24.082
-30.103
-36.124
-42.144
-48.165
-0.033996
-6.021
(dBFS)
2
GAIN
32
30
2
32
–
–
32
32
1]
) = 0.011Hz for the
) = 0.012Hz for the
SCALING GAIN
(V
99.6
50.0
25.0
12.5
OUT
6.25
3.125
1.5625
0.78125
0.390625
/V
IN
)%
(EQ. 6)