hsp50215 Intersil Corporation, hsp50215 Datasheet
hsp50215
Related parts for hsp50215
hsp50215 Summary of contents
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... Timing and Carrier NCO’s into a single package. Each DUC can create a single FDM channel. Multiple DUC’s can be cascaded digitally for multi-channel applications. The HSP50215 supports both vector and FM modulation. In vector modulation mode, the DUC accepts 16-bit I and Q samples to generate virtually any quadrature modulation format ...
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Functional Block Diagram CAS(1P5:0) CASZ † MOD (1:0) FM MOD † IIN(15:0) IFIFO † QIN(15:0) REFCLK QFIFO † RTH (2:0) RST † RST † MOD (1:0) WR † SR(29: ICOEFFICIENTS(15:0) C(15:0) QCOEFFICIENTS(15:0) A(9:0) † CF(31:0) † OUTGAIN (7:0) ...
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... REFCLK CAS8 18 CAS9 CAS10 CAS11 CAS12 CAS13 25 26 CAS14 27 CAS15 3-424 HSP50215 100 LEAD MQFP TOP VIEW OUT0 ...
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... Reset. When the RST input is asserted (dropped low), the DUC is reset and all processing halts. The DUC may also be reset on P command. Processing remains halted until a sync is generated either by P command or assertion of SYNCIN. See the Reset section details of the specific functions halted by this control signal. 3-425 HSP50215 DESCRIPTION , and is the rate at which data is output from the part. CLK ...
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... Functional Description The HSP50215 Digital UpConverter (DUC) converts digital baseband data into modulated or frequency translated digital samples. The DUC can be configured to create any quadrature amplitude shift-keyed (QASK) data modulated signal, including QPSK, BPSK, and m-ary QAM. The DUC can also be configured to create both shaped and unfiltered FM signals ...
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... The modulation format is selected using Control Word 16 (See the Microprocessor Write section). Control Word 16 bits (1:0) are defined as: 00:QASK, 01:FM 3-427 HSP50215 with post-modulation filtering, and 10:FM with pre- modulation pulse shaping. These modulation paths are defined in the following subsections. Modulation Mode 00 - QASK This modulation mode confi ...
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... F is defined as the sample rate into FM SAMP SAMP 3-428 HSP50215 modulator. The maximum phase step that can occur in one clock is 180 degrees. Table 1 provides the change in phase weighting of the input bits. TABLE 1. FM MODULATOR TRANSFER FUNCTION FILTER Shaping Filter The shaping fi ...
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... Gain OutGain 10 2 Hex = 3-429 HSP50215 where Gain is the desired signal level relative to fullscale, Gain dB and OutGain is the control word value. MAX f S Table 3 details a few key control words and the associated 52/256 = 203kHz attenuations for the I and Q signals. 52/128 = 406kHz ...
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... Common clocking of the PUC and PDC: Note that at a board level, the HSP50214 (PDC) and HSP50215 (DUC) sample rate NCO’s typically utilize different clocks. The DUC circuitry is clocked at the master clock, REFCLK, rate. The PDC output circuitry runs off the decimated sample rate ...
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... To avoid the phase glitch, noted above, the phase accumulator can be disabled at reset, and the frequency can be pre-loaded prior to asserting sync. 3-431 HSP50215 The maximum error is 52MHz/(2 commercial part and 0.011Hz for the industrial part. The carrier frequency can be calculated from the value loaded ...
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... The address map for these registers is given in the Configuration Control Register Bit Definition section. 3-432 HSP50215 Configuration data is written into the HSP50215 by setting up the address (A9:0) and data (C15:0) and generating a rising edge on WR. A DUC configuration sequence is shown in Figure 13. Figure 13 assumes that CE is asserted. The filter coefficients for the shaping filter are loaded in a similar manner into Control Word addresses 512 - 1023 ...
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... IP12 524 540 556 572 IP13 525 541 557 573 IP14 526 542 558 574 IP15 527 543 559 575 3-433 HSP50215 576 592 608 624 640 577 593 609 625 641 578 594 ...
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... Shaping filter Q coefficients are loaded from the first coefficient (B0) in address 0x300h to the last address in 0x3FFh. The convolution multiplies B0 by the most recent data sample. For a 16 tap, interpolate-by-4 filter, the calculations are: 3-434 HSP50215 TABLE 6. Q SHAPING FILTER COEFFICIENT ADDRESSES ...
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... FIFO Ready is the logical inverse of the FIFORDY output. I and Q FIFO empty bits are the output of a “zero” state detector operating on the address bus for the respective FIFO DON’T CARE xxxxxxxx xxxxxxxx A(9:0) C(15:0) HI-Z NOTE: See Table 8 for valid Read Addresses. 3-435 HSP50215 832 ...
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... Figure 16. When the first chip receives an input sync from a write to the LSByte of the timing NCO control word, then the SYNCOUT will synchronize all other DUC’s slaved to that chip. HSP50215 HSP50215 HSP50215 FIGURE 16. CONFIGURATION FOR SYNCHRONIZATION OF MULTIPLE DUCs SYNCOUT SYNCIN SYNCIN ...
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... Reserved (Note 1) 3 Enable Output 3-437 HSP50215 CONTROL ADDRESS 0: I CHANNEL INPUT IIN(15:0). In QASK mode, this is the I input vector. The format is 2’s complement. The MSB is bit 15. The mixer operation is: OUT = (I*COS) - (Q*SIN mode, this is interpreted as an offset frequency to the center frequency. The modulation index depends on the mode and the fi ...
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... MOD(1:0 QASK with filtering after modulation (analog FM with baseband filtering provided before HSP50215). In this mode, both I and Q filters are used with filtering before modulation (FSK, GMSK). This mode uses only the I filter bank not used. CONTROL ADDRESS 17: GAIN CONTROL Reserved ...
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... BIT POSITION FUNCTION 15:0 Q Coefficients NOTE: 1. Reserved bits should be set to logic 0. 3-439 HSP50215 CONTROL ADDRESS 20: SPARE Reserved (Note 1). CONTROL ADDRESS 21: RESET CONTROL RST. Writing to this registers will reset this part. CONTROL ADDRESS 22: SYNC CONTROL Reserved (Note 1). SYNCPOL. 0 defines a Sync assertion as a transition from a logic low to a logic high; 1 defines a Sync assertion ...
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... C, controlled via design or process parameters and not directly tested. Characterized upon initial design and at major pro- A cess or design changes. 3-440 HSP50215 Thermal Information Thermal Resistance (Typical, Note 2) +0.5V MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... V = 4.0V 0V. IH IHC IL 6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes. AC Test Load Circuit SWITCH S † TEST HEAD CAPACITANCE 3-441 HSP50215 5 Commercial SYMBOL t CP ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3-442 HSP50215 t WRH t ...