hsp50215 Intersil Corporation, hsp50215 Datasheet - Page 5

• Manufacturer Part Number: hsp50215
• Description: Digital Upconverter
• Manufacturer: Intersil Corporation

Functional Description
The HSP50215 Digital UpConverter (DUC) converts digital
baseband data into modulated or frequency translated digital
samples. The DUC can be configured to create any
quadrature amplitude shift-keyed (QASK) data modulated
signal, including QPSK, BPSK, and m-ary QAM. The DUC
can also be configured to create both shaped and unfiltered
FM signals. A minimum of 16 bits of resolution is maintained
throughout the internal processing.
The DUC is configured via the 16-bit microprocessor data
bus, using the address bus and RD, WR and CE control
signals. Configuration data that is loaded via this bus
includes the 30-bit Sample Rate NCO center frequency, the
32-bit Carrier NCO center frequency, the modulation format,
gain control, FIFO control, reset control and sync control.
The I and Q baseband channels each have a 256 tap FIR
filter whose coefficients and configuration are also
programmed via the P interface. Similarly, the control
signals for the I and Q channel interpolation filters are
programmed via the P interface. Once the operational
configuration for the device has been set, the 16-bit P
interface is used to input the I and Q data into the associated
FIFOs.
The FIFOs provide the data interface between the P and
either the FM modulator or the shaping filters. Multiplexers
route the I data to the FM modulator in the FM with
bandlimiting filter mode. Both I and Q are routed to the 256
tap FIR shaping filters in the QASK mode. The shaping filter
serves to both shape and interpolate the sample rate to 4, 8,
or 16 times the input sample rate. The I shaping filter output
can also be routed to the FM modulator for the FM with pulse
shaping mode. Multiplexers select either the FM modulator
output or the shaping filter output to be scaled and routed to
the interpolation filters.
The I and Q interpolation filters allow a non-integer increase in
sample rate, up to the reference clock rate. The interpolation
filter output data is upconverted or modulated by the Carrier
NCO and multipliers. The modulated signal is added to
modulated inputs from other cascaded DUC’s. The output
formatter sets the output buffer state and the output data
format.
Programmable FIFO
The Programmable FIFOs provide a data storage and
interface between the microprocessor data write holding
register and the shaping filter or the FM modulator. Signal
routing out of the FIFO is set by the modulation format. Each
FIFO has seven 16-bit registers. Figure 1 shows the
conceptual details of the I and Q FIFOs.
3-426
HSP50215
FM ENABLED
QIN(15:0)
WR SHFT EN
WR
A(000)
IIN(15:0)
WR
ZERO’S
RTH(2:0)
A(001)
WR
A(2:0)
WR
DLY DATA
FIFORDY
REFCLK
>
>
DFF 1
DFF 2
DFF 3
DFF 4
REG1
R
E
G
R
G
E
WR
FIGURE 2. FIFORDY AND DATA DELAY TIMING
FIGURE 1. I AND Q FIFO BLOCK DIAGRAM
>
>
R
G
E
FIFO NEEDS
MORE DATA
G
R
E
WRITE SHIFT ENABLE
DFF1
>
G
R
E
DFF1
>
>
>
R
E
G
G
R
E
WRITE SHIFT ENABLE
R
E
G
DFF2
>
G
R
E
DFF2
>
>
1
>
R
E
G
G
R
E
R
E
G
DFF3
>
G
R
E
2
8:1 MUX
8:1 MUX
DFF3
>
>
>
R
E
G
R
E
G
R
G
E
3
DFF4
>
R
G
E
DFF4
>
>
>
4
G
R
E
G
R
E
R
E
G
†
ARE CLOCKED AT
REFCLK UNLESS
SHOWN OTHERWISE
ALL REGISTERS
FIFO NEEDS
MORE DATA
>
>
R
E
G
R
G
E
IFIFO(15:0)
FIFORDY
QFIFO(15:0)
>
>
R
G
E
R
E
G