cp3cn23 National Semiconductor Corporation, cp3cn23 Datasheet - Page 137
cp3cn23
Manufacturer Part Number
cp3cn23
Description
Cp3cn23 Reprogrammable Connectivity Processor With Dual Can Interfaces
Manufacturer
National Semiconductor Corporation
Datasheet
1.CP3CN23.pdf
(246 pages)
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Data bits are sensed by taking a majority vote of three sam-
ples latched near the midpoint of each baud (bit time). Nor-
mally, the position of the samples within the baud is
determined automatically, but software can override the au-
tomatic selection by setting the USMD bit in the UnMDSL2
register and programming the UnSPOS register.
Serial data input on the RXD pin is shifted into the RSFT
register. On receiving the complete character, the contents
16
16
1
1
Sample
2
2
Generator/Checker
Figure 59. UART Asynchronous Communication
Error Detection
3
3
Control and
STARTBIT
Parity
DATABIT
4
4
Figure 58. UART Block Diagram
5
5
6
6
7
7
Transmitter
137
Receiver
8
8
System Clock
of the RSFT register are copied into the UnRBUF register
and the Receive Buffer Full bit (URBF) is set. The URBF bit
is automatically cleared when software reads the character
from the URBUF register. The RSFT register is not software
accessible.
Baud Rate
Generator
9
9
Sample
Sample
Baud Clock
Baud Clock
10
10
11
11
12
12
Flow Control
13
13
Logic
14
14
15
15
16
16
DATA (LSB)
DS060
DS061
TXD
RTS
CTS
CKX
RXD
1
1
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