LMH1982SQ National Semiconductor Corporation, LMH1982SQ Datasheet - Page 7

• Manufacturer Part Number: LMH1982SQ
• Manufacturer: National Semiconductor Corporation

Clock Outputs (Pins 19, 20, 23, 24)
Jitter
Jitter
|V
|V
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)
Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Note 3: The input voltage to VC_FREERUN (pin 1) should also be within the input range of the external VCXO. The input voltage should be clean from noise
that may significantly modulate the VCXO control voltage and consequently produce output jitter during free run operation.
Note 4: ΔT
within ΔT
4.2 Internal Reference Frame Decoder and 5.2.5 Output Frame Line Offset.
Note 5: The SD and HD clock output jitter is based on VCXO clock with 20 ps TIE peak-to-peak jitter. The TIE peak-to-peak jitter (typical) was measured on the
LMH1982 evaluation bench board using a Tektronix DSA70604 oscilloscope with TDSJIT3 jitter analysis software and 1 GHz differential probe.
TIE Measurement Setup: 10
varied with clock frequency.
Oscilloscope Setup: 20 mV/div vertical scale, 100 us/div horizontal scale, and 25 Gs/s sampling rate.
V
V
I
I
OS
OZ
OD
OS
OD
OS
SD
HD
|
|
HV
27 MHz Time Interval Error
(TIE) Peak-to-Peak Output
Jitter (Note 5)
27 MHz TIE Peak-to-Peak
Output Jitter(Note 5)
67.5 MHz TIE Peak-to-Peak
Output Jitter (Note 5)
74.176 MHz TIE Peak-to-Peak
Output Jitter (Note 5)
74.25 MHz TIE Peak-to-Peak
Output Jitter (Note 5)
148.35 MHz TIE Peak-to-Peak
Output Jitter (Note 5)
148.5 MHz TIE Peak-to-Peak
Output Jitter (Note 5)
Differential Signal Output
Voltage
Common Signal Output Voltage 100Ω Differential Load
|Change to V
Complementary Output States
|Change to V
Complementary Output States
Output Short Circuit Current
Output Hi-Z Leakage Current
HV
for all even fields and be outside ΔT
is required specification to allow for proper frame decoding and subsequent output alignment. For interlace formats, the H-V timing offset must be
OD
OS
-12
| for
| for
bit error rate (BER) and
HV
for odd fields. For progressive formats, the H-V timing offset must be within ΔT
HD_CLK = Hi-Z
HD_CLK = 74.176 MHz
HD_CLK = 74.176 MHz
SD_CLK = Hi-Z
SD_CLK = Hi-Z
SD_CLK = Hi-Z
SD_CLK = Hi-Z
100Ω Differential Load
100Ω Differential Load
100Ω Differential Load
V
CLK = Hi-Z, V
CLK
≈
and V
1M samples recorded over multiple acquisitions. The number of acquisitions to record
CLK
CLK
= GND
= V
DD
7
or GND
1.125
247
1.250
350
23
40
50
55
40
60
45
1
HV
for all frames. See sections
1.375
454
50
50
24
10
www.national.com
≈
1M samples
|mV|
|mV|
|mA|
|µA|
mV
ps
ps
ps
ps
ps
ps
ps
V