LMH1982SQ National Semiconductor Corporation, LMH1982SQ Datasheet - Page 17

• Manufacturer Part Number: LMH1982SQ
• Manufacturer: National Semiconductor Corporation

6.2.2 PLL Lock Status Instability
It is possible for excessive jitter on the H input to indicate lock
instability through the NO_LOCK output, even if VCXO PLL
and output clocks are properly phase locked and no system-
level errors are occurring (e.g. bit errors). To reduce the
probability of false loss of lock indication or lock status insta-
bility, LOCK_CTRL can be increased to improve the lock
detector’s ability to tolerate a larger amount of input phase
jitter or phase error. This can help to ensure the NO_LOCK
output and SD_LOCK bit are stable when the reference signal
has large input jitter.
7.0 VCXO PLL LOOP RESPONSE
The overall jitter performance of the LMH1982 is determined
by the design of the VCXO PLL's loop response. Because the
integrated VCO PLLs use the VCXO clock as the input refer-
ence to phase lock the output clocks, the ability of the VCXO
PLL to attenuate the input jitter is critical. The loop response
can be characterized by its loop bandwidth and damping fac-
tor. A lower loop bandwidth will provide higher input jitter
attenuation (reduced jitter transfer) for improved output jitter
characteristics. Increased lock time (or settling time) and larg-
er external component values are a couple trade-offs to hav-
ing a lower loop bandwidth.
The loop response is primarily determined by the loop filter
components and the loop gain. A passive second-order loop
filter consisting of R
sufficient input jitter attenuation for most applications, al-
though a higher order passive filter or active filter may also be
used. The loop gain is a function of the VCXO gain and pro-
grammable PLL parameters.
7.1 Loop Response Design Equations
The following equations can be used to design the loop re-
sponse of the VCXO PLL.
The -3 dB loop bandwidth, BW, can be approximated by:
Where:
Note that this BW approximation does not take into account
the effects of the damping factor or the second pole intro-
duced by Cp.
At frequencies far above the −3 dB loop bandwidth, the
closed-loop frequency response of the VCXO PLL will roll off
I
R
K
FB_DIV = Feedback Divider value
CP1
VCO
BW = I
S
=
=
=
CP1
Nominal VCXO PLL charge pump current (in
amps)
programmed by setting ICP1 (register 13h).
For example:
I
I
I
I
I
Nominal value of series resistor (in ohms)
Nominal 27 MHz VCXO gain (in Hz/V)
K
For the recommended VCXO (CTS
357LB3I027M0000): K
(3.0V- 0.3V) = 1000 Hz/V
For example:
FB_DIV =1716 for NTSC Hsync input
CP1
CP1
CP1
CP1
CP1
* R
VCO
S
= 250 µA: ICP1 = 08h (default value)
= 0 µA: ICP1 = 00h (min)
= 62.5 µA; ICP1 = 02h (practical min)
= 968.75 µA; ICP1 = 1Fh (max)
step size = 31.25 µA
* K
= Pull_range * 27 MHz/Vin_range
S
VCO
, C
S
/ FB_DIV
, and C
P
VCO
components can provide
= 100 ppm * 27 MHz/
17
at about −40 dB/decade, which is useful attenuating input jit-
ter at frequencies above the loop bandwidth. Near the −3 dB
corner frequency, the roll-off will depend on other factors,
such as damping factor and filter order.
To prevent output jitter due to the modulation of the VCXO by
the PLL’s phase comparison frequency:
The VCXO PLL damping factor, DF, can be approximated by:
Where:
A typical design target for DF is between 0.707 to 1, which
can often yield a good trade-off between reference spur at-
tenuation and lock time. DF is related to the phase margin,
which is a measure of the PLL stability.
A secondary parallel capacitor, C
erence spurs introduced by the PLL which may modulate the
VCXO input voltage and also cause output jitter. The following
relationship should be used to determine C
The PLL loop gain, K, can be calculated as:
Therefore, the BW and DF can be expressed in terms of K:
7.1.1 Loop Response Optimization Tips
To design and optimize the PLL response for a given loop
filter across all input reference formats, it is suggested to
maintain a relatively constant loop gain, K, across all expect-
ed values for FB_DIV. It is desirable to maintain a narrow
range for K because the term K affects both BW and DF
equations. To maintain a relatively constant K, I
adjusted in proportion to the change in FB_DIV.
It is suggested to design for the loop filter component values
using the BW and DF equations and initially assuming
FB_DIV = 1716 (NTSC) and I
Once reasonable component values are achieved under
these initial assumptions, it is necessary to check that K can
be maintained over the expected range of FB_DIV by adjust-
ing I
practical minimum of 62 µA (ICP1 = 2) to a maximum of 969
µA (ICP1 = 31), so it should provide adequate adjustment
range to maintain a relatively constant value for K assuming
the suggested starting values for FB_DIV and I
lowed. If a narrow range for K cannot be maintained within the
usable range of I
be modified.
In some loop response design, the calculated I
is required for a target K value can be near or below the prac-
tical minimum of the I
may be possible to leverage the programmable VCXO PLL
reference and feedback dividers by scaling up the values in
proportion (i.e. same reduced divider ratio); this would allow
I
current range. This technique of scaling FB_DIV and I
sumes that the reference format has more than one combi-
nation of compatible divider values as explained in the latter
part of section 4.1 Programming The VCXO PLL Dividers.
CP1
BW
DF = (R
C
C
K = I
BW = R
DF = (R
S
P
to be scaled up by the same factor to be within the usable
CP1
= Nominal value of the series capacitor (in farads)
= C
≤
CP1
. The usable current range of I
(27 MHz / FB_DIV) / 20
S
S
S
S
/ 20
* K
/2) * sqrt (C
* K
/ 2) * sqrt (I
VCO
CP1
/ FB_DIV
, then the loop filter design may need to
CP1
S
CP1
* K)
current range. In these situations, it
* C
S
CP1
* K
P
= 250 µA (default setting).
, is needed to filter the ref-
VCO
/ FB_DIV)
CP1
P
:
CP1
is limited to a
CP1
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current that
CP1
were fol-
can be
CP1
as-