LMH1982SQ National Semiconductor Corporation, LMH1982SQ Datasheet - Page 16

• Manufacturer Part Number: LMH1982SQ
• Manufacturer: National Semiconductor Corporation

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6.0 REFERENCE AND PLL LOCK STATUS
Notes
1. NO_REF output = REF_VALID
2. NO_LOCK output = (REF_VALID) (SD_LOCK) (HD_LOCK)
The LMH1982 features a reference detector and PLL lock
detector that can be used to indicate genlock status of the
input reference and device PLLs. Genlock status can be sam-
pled via the NO_REF and NO_LOCK output status pins and
the REF_VALID, SD_LOCK, and HD_LOCK status bits (reg-
ister 01h). Both the reference and PLL lock detectors may be
programmed for their respective detection thresholds accord-
ing to the needs of the application system.
6.1 Reference Detection
In Genlock mode, a valid reference will be indicated by
NO_REF = 0 when all the criteria below are met. Otherwise,
a loss of reference (LOR) will be indicated by NO_REF = 1.
The NO_REF output is the logical NOT of the REF_VALID
status bit.
•
•
•
6.1.1 Programming the Loss of Reference (LOR)
Threshold
The reference detector's error threshold can be programmed
to H_ERROR (register 00h), which determines the maximum
number of missing H sync pulses before indicating an LOR.
The LOR threshold will be the H_ERROR value multiplied by
the PLL reference divider value, as shown in Table 9.
If H_ERROR = 0, then the device will react after the first miss-
ing pulse. When the LOR threshold is exceeded, the NO_REF
output will indicate LOR, and the device will default to either
Free Run or Holdover operation for as long as the reference
is lost. As the LOR threshold value is increased, the accuracy
Genlock mode, Reference
valid, PLLs locking
Genlock mode, Reference
valid, PLLs locked
Genlock mode, Reference
lost, Free Run operation
Genlock mode, Reference
lost, Holdover operation
Register 03h
An H sync signal is applied to the input reference and
conforms to one of the standard formats in Table 2. A
V sync signal is not used in reference detection.
The PLL divide registers are programmed according to the
input reference format.
The control voltage of the VCXO is not within about 500
mV of the GND or V
REF_DIV
00b
01b
10b
Conditions
TABLE 9. LOR Threshold Selection
Divider Value
Reference
DD
supplies.
2
1
5
TABLE 8. Summary of Genlock Status Bits and Flag Outputs
Mode Control Bits
GNLK
Register 00h
1
1
1
1
LOR Threshold
2 x H_ERROR
1 x H_ERROR
5 x H_ERROR
HOLD-
OVER
X
X
0
1
NO_REF
(pin 16)
Status Flag Outputs
0
0
1
1
16
1
for counting the actual number of missing H pulses may di-
minish due to frequency drifting by the VCXO PLL.
Note: If the input reference is missing H pulses periodically,
e.g. every vertical interval period, the PLL may not indicate a
valid reference nor achieve lock regardless of the H_ERROR
value programmed. This is because periodically missing puls-
es will translate to a lower average frequency than expected.
When the average input frequency falls outside of the abso-
lute pull range (APR) of the VCXO, the PLL will not be able to
frequency lock to the input reference.
6.2 PLL Lock Detection
In Genlock mode, PLL lock will be indicated by NO_LOCK =
0 when all the criteria below are met. Otherwise, a loss of lock
will be indicated by NO_LOCK = 1.
The NO_LOCK output is the logical NAND of the REF_VALID,
SD_LOCK, and HD_LOCK status bits.
•
•
•
The VCO PLLs have high loop bandwidths, which allow them
to achieve lock quickly and concurrently while the VCXO PLL
achieves lock. Because the VCXO PLL has a much lower loop
bandwidth, it will dictate the overall lock indication time.
6.2.1 Programming the PLL Lock Threshold
The VCXO PLL lock detector threshold can be programmed
to LOCK_CTRL (register 01h), which determines the maxi-
mum phase error between PLL 1's phase detector (PD) inputs
before indicating an unlock or lock condition. The PD inputs
are the reference signal (H sync input / reference divider) and
the feedback signal (VCXO clock / feedback divider).
The lock detector will indicate loss of lock when the phase
error between the PD inputs is greater than the lock threshold
for three consecutive phase comparison periods. Conversely,
it will indicate valid lock when the phase error is less than the
lock threshold for three consecutive phase comparison peri-
ods.
A larger value for LOCK_CTRL will yield shorter lock indica-
tion time (although not actual lock time) at the expense of
higher output phase error when lock is initially indicated,
whereas a smaller value will yield the opposite effect.
NO_LOCK
A valid reference is indicated (REF_VALID = 1).
The VCXO PLL is phase locked to the input reference
(SD_LOCK = 1).
The relevant HD clock VCO PLL is phase locked to the
VCXO clock reference (HD_LOCK = 1).
(pin 17)
1
0
1
1
2
HD_LOCK
bit 2
0
1
1
1
Register 01h
Status Bits
SD_LOCK
bit 1
0
1
0
0
REF_VALID
bit 0
1
1
0
0