gs8160e32bt-250v GSI Technology, gs8160e32bt-250v Datasheet - Page 19
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gs8160e32bt-250v
Manufacturer Part Number
gs8160e32bt-250v
Description
1m X 18, 512k X 32, 512k X 36 18mb Sync Burst Srams
Manufacturer
GSI Technology
Datasheet
1.GS8160E32BT-250V.pdf
(23 pages)
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs (like this one) do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
Rev: 1.01 5/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ADSC
ADSP
CK
ZZ
Setup
Hold
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
tKC
tKC
tKH
tKH
tKL
tKL
Sleep Mode Timing
19/23
tZZS
tZZH
tZZR
GS8160ExxBT-xxxV
SB
© 2004, GSI Technology
2. The duration of
Preliminary