gal16v8z-15qs Lattice Semiconductor Corp., gal16v8z-15qs Datasheet - Page 6

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gal16v8z-15qs

Manufacturer Part Number
gal16v8z-15qs
Description
Gal Zero Power E2cmos Pld
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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In the Complex mode, macrocells are configured as output only or
I/O functions.
Architecture configurations available in this mode are similar to the
common 16L8 and 16P8 devices with programmable polarity in
each macrocell.
Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 12 & 19) do not have input capability. De-
signs requiring eight I/Os can be implemented in the Registered
mode.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Complex Mode
XOR
XOR
6
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
11 are always available as data inputs into the AND array.
Pin 4 is used as dedicated power-down pin on GAL16V8ZD. It can-
not be used as functional input.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
Combinatorial I/O Configuration for Complex Mode
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 13 through Pin 18 are configured to this function.
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 12 and Pin 19 are configured to this
function.
Specifications GAL16V8Z
GAL16V8ZD

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