gal16v8z-15qs Lattice Semiconductor Corp., gal16v8z-15qs Datasheet
gal16v8z-15qs
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gal16v8z-15qs Summary of contents
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... State Machine Control — High Speed Graphics Processing • ELECTRONIC SIGNATURE FOR IDENTIFICATION Description The GAL16V8Z and GAL16V8ZD, at 100 A standby current and 12ns propagation delay provides the highest speed and lowest DESCRIPTION power combination PLD available in the market. The GAL16V8Z/ ...
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... Speed (ns) Active Power Q = Quarter Power Specifications GAL16V8Z Isb ( A) Ordering # 55 100 GAL16V8Z-12QP 55 100 GAL16V8Z-12QJ 55 100 GAL16V8Z-12QS 55 100 GAL16V8Z-15QP 55 100 GAL16V8Z-15QJ 55 100 GAL16V8Z-15QS Isb ( A) Ordering # 55 100 GAL16V8ZD-12QP 55 100 GAL16V8ZD-12QJ 55 100 GAL16V8ZD-15QP 55 100 GAL16V8ZD-15QJ _ XXXXXXXX GAL16V8ZD Package 20-Pin Plastic DIP 20-Lead PLCC ...
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... When using the standard GAL16V8 JEDEC fuse pattern generated by the logic compilers for the GAL16V8ZD, special attention must be given to pin 4 (DPP) to make sure that it is not used as one of the functional inputs. ...
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... Specifications GAL16V8Z Registered outputs have eight product terms per output. I/Os have seven product terms per output. Pin 4 is used as dedicated power-down pin on GAL16V8ZD. It cannot be used as functional input. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page ...
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... Byte1 Byte0 5 GAL16V8ZD OLMC 19 XOR-2048 AC1-2120 OLMC 18 XOR-2049 AC1-2121 OLMC 17 XOR-2050 AC1-2122 OLMC 16 XOR-2051 AC1-2123 OLMC 15 XOR-2052 AC1-2124 OLMC 14 XOR-2053 AC1-2125 OLMC 13 XOR-2054 AC1-2126 OLMC 12 XOR-2055 AC1-2127 OE 11 SYN-2192 AC0-2193 * Note: Input not available on GAL16V8ZD ...
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... Pins 1 and 11 are always available as data inputs into the AND array. Pin 4 is used as dedicated power-down pin on GAL16V8ZD. It can- not be used as functional input. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page ...
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... PTD 2191 .... 2118, 2119 .... Byte1 Byte0 LSB 7 GAL16V8ZD OLMC 19 XOR-2048 AC1-2120 OLMC 18 XOR-2049 AC1-2121 OLMC 17 XOR-2050 AC1-2122 OLMC 16 XOR-2051 AC1-2123 OLMC 15 XOR-2052 AC1-2124 OLMC 14 XOR-2053 AC1-2125 OLMC 13 XOR-2054 AC1-2126 OLMC 12 XOR-2055 AC1-2127 11 SYN-2192 AC0-2193 * Note: Input not available on GAL16V8ZD ...
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... Pins 1 and 11 are always available as data inputs into the AND array. The center two macrocells (pins 15 & 16) cannot be used in the input configuration. Pin 4 is used as dedicated power-down pin on GAL16V8ZD. It can- not be used as functional input. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram ...
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... PTD 2191 .... 2118, 2119 .... Byte1 Byte0 LSB 9 GAL16V8ZD OLMC 19 XOR-2048 AC1-2120 OLMC 18 XOR-2049 AC1-2121 OLMC 17 XOR-2050 AC1-2122 OLMC 16 XOR-2051 AC1-2123 OLMC 15 XOR-2052 AC1-2124 OLMC 14 XOR-2053 AC1-2125 OLMC 13 XOR-2054 AC1-2126 OLMC 12 XOR-2055 AC1-2127 11 SYN-2192 AC0-2193 * Note: Input not available on GAL16V8ZD ...
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... -100 A Vin = 0.5V CC OUT = GND V = Vcc Outputs Open 0. 3. MHz Outputs Open = MAXIMUM Specifications GAL16V8Z GAL16V8ZD ) ............................... MIN. TYP. 2 — Vss – 0.5 2.0 — — — — — — — 2.4 — ...
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... Add sa to pd, su, en and dis when the device is coming out of standby state. Standby Power Timing Waveforms Icc POWER Isb INPUT or I/O FEEDBACK OE CLK OUTPUT Specifications GAL16V8Z Specifications GAL16V8Z Over Recommended Operating Conditions GAL16V8ZD COM COM -12 -15 MIN. MAX. ...
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... C Input or I/O to Output Disabled Output Disabled 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section. Specifications GAL16V8ZD Over Recommended Operating Conditions 12 COM COM -12 -15 UNITS MIN. MAX. MIN. MAX. ...
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... DPP Low to Valid Clock t dlov A DPP Low to Valid Output 1) Refer to Switching Test Conditions section. Dedicated Power-Down Pin Timing Waveforms DPP INPUT or I/O FEEDBACK OE CLK OUTPUT Specifications GAL16V8ZD Over Recommended Operating Conditions t t ivdh dhix t t gvdh dhgx t t cvdh dhcx t ...
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... Clock Width INPUT or I/O FEEDBACK VALID INPUT t pd CLK REGISTERED OUTPUT REGISTERED OUTPUT t wl CLK REGISTERED FEEDBACK 14 Specifications GAL16V8Z GAL16V8ZD VALID INPUT max (external fdbk) Registered Output t t dis Output Enable/Disable f 1/ max (internal fdbk) ...
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... GND to 3.0V 3ns 10% – 90% 1.5V 1.5V See Figure FROM OUTPUT (O/Q) UNDER TEST R2 CL 390 50pF 390 50pF 390 50pF 390 5pF 390 5pF 15 Specifications GAL16V8Z GAL16V8ZD CLK LOGIC ARRAY REGISTER max with Internal Feedback 1/( su+ + ...
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... NOTE: The electronic signature is included in checksum calcu- lations. Changing the electronic signature will alter checksum. Security Cell A security cell is provided in the GAL16V8Z/ZD devices to pre- vent unauthorized copying of the array patterns. Once pro- grammed, this cell prevents further read access to the functional bits in the device ...
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... Vcc CLK t pr asynchronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the GAL16V8Z/ZD. First, the V pr MAX result, must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of normal system operation, avoid clocking the device until all in- put and feedback path setup times have been met ...
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... FALL - Number of Outputs Switching Delta Tco vs Output Loading 10 RISE 8 FALL 100 150 200 250 300 0 Output Loading (pF) 18 Specifications GAL16V8Z GAL16V8ZD Normalized Tsu vs Vcc 1.4 RISE 1.3 FALL 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.50 Supply Voltage (V) Normalized Tsu vs Temp 1.4 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 0.8 0.7 Temperature (deg. C) Switching ...
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... Normalized Icc vs Temp 1.2 1.1 1 0.9 0.8 5.50 -55 - Temperature (deg. C) Input Clamp (Vik -1.00 -0.80 -0.60 -0.40 -0.20 Vik (V) 19 Specifications GAL16V8Z GAL16V8ZD Voh vs Ioh 5 4.5 4 3.5 3 2.5 0.00 1.00 2.00 Ioh(mA) Normalized Icc vs Freq. (DPP & ITD > 10MHz) 1.30 1.20 1.10 1.00 0.90 0.80 100 125 Frequency (MHz) Normalized Icc vs Freq. (ITD) 1 0.8 0.6 0.4 ...