net2890 ETC-unknow, net2890 Datasheet - Page 28

• Manufacturer Part Number: net2890
• Description: Interface Controller
• Manufacturer: ETC-unknow

Specification
4.6 FIFOs
The NET2890 contains four 128-byte FIFOs, one associated with each data endpoint A-D. The direction of
the FIFO is determined by the Endpoint Direction bit (IN, OUT) of the endpoint. In addition, there is a 16
byte bi-directional FIFO dedicated for Control transfers, which is associated with Endpoint 0. The direction
of FIFO 0 is determined by the most significant bit of the first setup byte.
Each of the FIFOs has programmable threshold registers. Interrupts can be generated for the FIFO Almost
Empty Interrupt or FIFO Almost Full Interrupt conditions. If a FIFO becomes full, write cycles are
ignored until space becomes available again. Reads from an empty FIFO produce undefined data.
There is space in the 128-byte FIFOs for multiple BULK or INTERRUPT packets. Each endpoint has a set
of maximum packet size registers (EPnPKTSIZLSB, EPnPKTSIZMSB) which should be programmed
with the same value that is returned to the host in the Endpoint Descriptor (bytes 4 and 5).
4.6.1 IN FIFOs
The FIFO Valid bit determines the response (data or NAK) to an IN token when the FIFO Valid Mode bit
is set. The FIFO Valid bit is set by either the CPU or automatically at the end of a DMA. When there are
at least EPnPKTSIZ bytes in the FIFO, the data is automatically validated, and will be sent in response to
the next IN token. The NET2890 will not send more than EPnPKTSIZ bytes per packet. The local CPU can
continue loading data for the next packet until the FIFO is full, and the NET2890 will automatically divide
the data flow into EPnPKTSIZ packets. This allows USB transfers to overlap with loading of data from the
local bus.
The local CPU should only set FIFO Valid when it wants to send a short or zero-length packet (indicating
end of transfer). If more data is loaded after FIFO Valid is set but before the next IN token occurs, that
data will be included in response to the IN token. If enough data is added to make EPnPKTSIZ bytes or
more, EPnPKTSIZ bytes will be sent in the next packet and FIFO Valid will not be cleared. FIFO Valid
is cleared only when a short or zero-length packet is successfully sent to the host. It is also cleared by a
local reset, USB reset, FIFO flush, or if the endpoint type is changed from IN to OUT.
End of transfers are indicated by short (less than EPnPKTSIZ) or zero-length packets. If FIFO Valid Mode
is true, the NET2890 will send a short or zero length packet only if the local CPU has set the FIFO Valid
bit.
If a short packet has been loaded into the FIFO and the FIFO Valid bit has been set, additional data written
to the FIFO before the completion of the USB data packet is included in the current packet. If the
additional data results in a packet size of EPnPKTSIZE or greater, then the original short packet will have
been converted to a maximum size packet, and the FIFO Valid bit will not be cleared until a short or zero
length packet is transferred.
During DMA transfers, if the number of bytes transferred is an integer multiple of the maximum packet
size, then a zero length packet will always be sent following the DMA data. This happens because the
FIFO Valid bit is always set at the end of a DMA transfer, and the FIFO will be empty in this case.
If FIFO Valid Mode is false, and there are fewer than EPnPKTSIZ bytes in the FIFO, the NET2890 will
send whatever is currently in the FIFO in response to the next IN token even if FIFO Valid has not been
set. Zero length packets can be sent by setting the FIFO Valid bit when the FIFO is empty.
____________________________________________________________________________________
335 Pioneer Way, Mountain View, California 94041
TEL [phone] FAX [phone]
NetChip Technology, Inc., 1999
Rev 2.0, Draft 9, July 16, 1999
http://www.netchip.com
NET2890 USB Interface Controller
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