net2890 ETC-unknow, net2890 Datasheet - Page 22

• Manufacturer Part Number: net2890
• Description: Interface Controller
• Manufacturer: ETC-unknow

Specification
During a control read operation, optional Data transactions can follow the Setup transaction. After the Setup
transaction, the local CPU can start writing the first byte of packet data into the Endpoint 0 FIFO in
anticipation of the Data transaction. The Data In Token Interrupt status bit is set at the beginning of each
Data transaction. If this interrupt is enabled, the local interrupt IRQ# pin is asserted. If there is data in the
Endpoint 0 FIFO, it is returned to the host. If Endpoint 0 has no data to return, it returns either a zero
length packet (signaling that there is no more data available) or a NAK handshake (the data is not available
yet), depending on the FIFO Valid and FIFO Valid Mode bits.
FIFO
Valid
Mode
0
0
0
0
0
1
1
1
1
After each packet has been sent to the host, the Data Packet Transmitted Interrupt status bit is set. If this
interrupt is enabled, the local interrupt IRQ# pin is asserted. If retries are disabled, the local CPU should
check the USB IN ACK Sent, USB IN NAK Sent, and Timeout status bits to determine if the packet was
successfully transmitted.
After all of the optional Data transaction packets have been transmitted, the host will send an OUT token,
followed by a zero length data packet, signifying the Status transaction. The Control Status Interrupt
status bit is set after the OUT token of the Status transaction has been received. If this interrupt is enabled,
the local interrupt IRQ# pin is asserted. Until the Control Status Phase Handshake bit is cleared by the
local CPU, the NET2890 will respond to the Status transaction with NAKs, indicating that the device is still
processing the command specified by the Setup transaction. When the Control Status Phase Handshake
bit has been cleared by the local CPU, the NET2890 will respond with an ACK (transfer OK) or STALL
(Endpoint 0 is stalled).
____________________________________________________________________________________
If a packet is not successfully transmitted (Timeout status bit set) and retries are enabled, the Data
Packet Transmitted Interrupt status bit will not be set, and the same packet is sent to the host when
another IN token is received. The retry operation is transparent to the local CPU.
If a packet is not successfully transmitted (Timeout status bit set) and retries are disabled, the Data
Packet Transmitted Interrupt status bit will be set. The local CPU needs to flush the FIFO and
reload the packet for the next IN token.
If the host tries to read more data than was requested in the setup packet, the local CPU should set the
STALL bit for the endpoint.
FIFO
Valid
Bit
0
0
0
1
X
0
X
1
1
End of
Transfer
Response Bit
0
1
1
X
X
X
X
X
X
335 Pioneer Way, Mountain View, California 94041
TEL [phone] FAX [phone]
Size of
Previous
Packet
X
Maximum
< Maximum
X
X
X
X
X
X
NetChip Technology, Inc., 1999
Rev 2.0, Draft 9, July 16, 1999
http://www.netchip.com
Amount of Data in
FIFO
empty
empty
empty
empty
>0
< Max Packet Length
>= Max Packet Length
empty
>0
NET2890 USB Interface Controller
Action
NAK to host
Zero length packet to host
NAK to host
Zero length packet to host
Return data to host
NAK to host
Return data to host
Zero length packet to host
Return data to host
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