net2890 ETC-unknow, net2890 Datasheet - Page 12

• Manufacturer Part Number: net2890
• Description: Interface Controller
• Manufacturer: ETC-unknow

Specification
1.5.3 Functional Changes
1.5.4 Documentation Changes
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Each of the four data endpoints (A-D) has a 128 byte FIFO permanently associated with it.
FIFOs 5-7 are obsolete: each endpoint has a FIFO attached to it (FIFO A - D), and each endpoint may
be configured as an IN or an OUT endpoint.
There is a separate 16 byte FIFO (FIFO 0) for Endpoint 0 (the default control pipe).
There is no second bank of SETUP registers.
“Packet Transmitted” interrupt (in EPIRQSTAT) only occurs when data is transmitted to the host
There is no interrupt when the NET2890 responds with a NAK or STALL to the host.
FIFO registers are grouped into the same page as the corresponding endpoint, instead of separate
pages.
FIFOs A-D increased to 128 bytes. Corresponding threshold and count registers increased to 8 bits.
Failed packets are automatically retried. If retries are enabled and a packet transfer fails, no interrupt or
status information in the NET2890 changes.
FIFO_VALID_MODE and FIFO_VALID can be used to generate zero-length-packets when required.
An interrupt (Control Status Phase) can be generated when the host begins a control status phase.
The new DIAG register can be used to artificially generate USB error conditions.
Instead of referring to “Physical” endpoints 1-4 and “Logical” endpoints 1-4, the local side will access
endpoints as Endpoints A-D. Endpoints A-D may each be mapped to any available endpoint address (1-
15), in any direction.
References to “Mapped” registers are all changed to “Paged”.
335 Pioneer Way, Mountain View, California 94041
TEL [phone] FAX [phone]
NetChip Technology, Inc., 1999
Rev 2.0, Draft 9, July 16, 1999
http://www.netchip.com
NET2890 USB Interface Controller
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