isppac20 Lattice Semiconductor Corp., isppac20 Datasheet - Page 8

• Manufacturer Part Number: isppac20
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Connection Notes
1.
2.
3.
Pin Descriptions
11, 19, 34
39, 6, 23
44, 1, 2,
26 to 33
3, 9, 10
TQFP
21, 22
24, 25
35, 36
4, 5,
7, 8
All inputs and outputs are labeled with plus (+) and minus (-) signs. Polarity is labeled for reference and can be selected externally by
reversing pin connections or internally under user programmable control.
All analog output pins are “hard-wired” to internal output devices and should be left open if not used. Outputs of uncommitted PACblocks
are forced to VREF
as unnecessary power will be dissipated.
When the signal input is single-ended, the other half of the unused differential input must be connected to a DC common-mode reference
(usually VREF
40
43
42
41
12
13
14
15
16
17
18
20
37
38
Pin(s)
17, 25, 40
6, 7, 8, 9,
32 to 39
1,12,29
10, 11,
PLCC
15, 16
13, 14
27, 28
30, 31
41, 42
18
19
20
21
22
23
24
26
43
44
2
5
4
3
OUT
, 2.5V).
OUT
WINDOW
DACOUT
Symbol
VREFout
D0 to D7
DMODE
CPOUT
(2.5V) and can be used as low impedance reference output buffers. V
ENSPI
CMVin
MSEL
TEST
CPIN
GND
OUT
TMS
TDO
TCK
CAL
TDI
VS
PC
CS
IN
Inputs 1, 2, 3 (+ or -)
Optional VREF OUT
Outputs 1,2 (+ or -)
Multiplexer Control
Comparator Inputs
DAC Mode Select
Enable SPI Mode
Test Mode Select
DAC Data Inputs
Factory Test pin
Common-Mode
Polarity Control
Supply Voltage
Auto-Calibrate
Test Data Out
Plus or minus
DAC Outputs
Test Data In
Comparator
Chip Select
Test Clock
Reference
Input for
Window
Outputs
Ground
Name
(+ or -)
Ground pins. All should normally be connected to same analog ground
plane.
Common-mode voltage reference output pin (+2.5V nominal). Must be
bypassed to GND with a 1 F capacitor.
Multiplexer logic input pin. Selects either of two analog channels to
one of the PACblock inputs. Input A selected when low, B when high.
Internal pull-down to GND.
Enable SPI logic input pin. When high, causes serial port to run in SPI
mode. Internal pull-down to GND.
Factory Test pin. Connect to GND for proper circuit operation.
Differential input pins, with two pins per input (e.g., IN2+ and IN2-).
Differential output pins, with two pins per output (e.g., OUT2+ and
OUT2-). Complementary with respect to VREF
V
Analog supply voltage pins (5V nominal). Must all be connected
together. Should all be bypassed to GND with 1 F and .01 F
capacitors.
Serial interface logic pin (input) for both JTAG and SPI modes. Input
data valid on rising edge of TCK (JTAG). Internal pull-up to V
Serial interface logic mode select pin (input). JTAG interface mode
only. Internal pull-up to V
Serial interface logic clock pin (input).
Polarity logic input pin. Controls polarity of one PACblock input.
Operation determined by user configuration of device. Internal
pull-down to GND.
Chip select logic input pin. SPI data and DAC parallel interface clock.
Internal pull-up to V
Serial interface logic pin (output) for both JTAG and SPI operation
modes. Output data valid on falling edge of TCK (JTAG).
DAC mode logic input. When high, DAC can be loaded via the parallel
interface pins D0-D7 using CS as the latch command. Internal pull-
down to GND.
Window comparison logic pin (output). Configured by user to
Comparator Outperform comparator logic functions.
Comparator logic pins (outputs). One pin for logic level of each
comparator.
Differential input pins, CPIN+ and CPIN-. Plus and minus components
of V
DAC data pins (inputs). Eight parallel inputs to DAC. Clocked
by CS pin. D0 is the LSB and D7 is the MSB.
Differential output pins (DOUT+ and DOUT-). Complementary with
respect to VREFout, where differential D
Input pin for optional analog Common Mode Output Voltage (CMVin).
Replaces VREFout (+2.5V) with this voltage for any user-selected
PACblock.
Digital pin (input). Commands an auto-calibration sequence on
a rising edge. Internal pull-down to GND.
8
components of V
OUT
IN
= V
, where differential CP
OUT+
- V
Specifications ispPAC20
OUT-
IN
, where differential V
S
.
.
S
Description
.
IN
OUT+
= CP
and V
IN+
- CP
OUT-
IN
OUT
= V
IN-
should not be tied together
= D
.
IN+
OUT
OUT+
- V
, where differential
IN-
- D
.
OUT-
.
S
.