isppac20 Lattice Semiconductor Corp., isppac20 Datasheet
isppac20
Related parts for isppac20
isppac20 Summary of contents
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... Analog Front Ends, 12-Bit Data Acq. Systems — Precision Voltage Controlled Oscillator — Synchronous Detection Circuits — Precision Rectification & Other Non-Linear Functions Description The ispPAC20 is a member of the Lattice family of In- System Programmable analog circuits, digitally configured 2 via nonvolatile E CMOS technology. ...
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... Bandwidth Bypass Capacitor 1kHz Guaranteed Monotonic - OUT+ OUT- Differential at 1kHz -40 to +85 C DAC Code 00h to FFh Differential L Source/Sink 0.1% 6V Input Step DIFF 2 Specifications ispPAC20 4V; Gain = 1; Output load OUT MIN. TYP. MAX. UNITS IN+ IN– 100 0.2 1 ...
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... OUT 0.1% 6V Input Step DIFF Between Any Two Channels Number of Poles in Range > 120 Deviation From Calculated Value 10kHz to 100kHz - (5) Includes TDO, CP1OUT, CP2OUT and WINDOW output logic pins. OUT 3 Specifications ispPAC20 MIN. TYP. MAX. 108 750 150 0 5.0 60 ...
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... Note: Stresses above those listed may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sec- tions of this specification is not implied. ispPAC20 Ordering Information Ordering Number ispPAC20-01JI ispPAC20-01TI 6 ...
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... Also, any configuration of the comparators that modifies their mode of operation (e.g., hysteresis on, clocked output mode, etc) can alter output states from initial settings until additional external conditions are reapplied to the device. Specifications ispPAC20 CONDITION Executed in Run-Test/Idle ...
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... DAC Data Hold Time tdozx TDO Float to Valid Delay tdov TDO Valid Delay tdoxz TDO Valid to Float Delay Timing Specifications (SPI Interface Mode) trenc tfenc ENSPI TCK CS TDI TDO Specifications ispPAC20 CONDITION tckmin tckh tckl tcss tdis tdih tdozx tdov hi-z 6 MIN. TYP. MAX. UNITS 10 ...
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... SPI data is loaded in TDI, LSB first. If TCK continues to clock after CS goes high, data will continue to be shifted through the shift register, 1. even though the TDO pin is tristated after CS goes high –> DO represents “data out” from the SPI microprocessor or other digital source to the TDI input of the ispPAC20 –> DI represents “ ...
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... Input pin for optional analog Common Mode Output Voltage (CMVin). Optional VREF OUT Replaces VREFout (+2.5V) with this voltage for any user-selected PACblock. Auto-Calibrate Digital pin (input). Commands an auto-calibration sequence on a rising edge. Internal pull-down to GND. 8 Specifications ispPAC20 Description , where differential ...
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... Frequency (Hz) Small Signal BW vs. Gain -15 -21 -27 -33 -39 1k 10k 100k 1M 10M Frequency (Hz) Capacitive Load Handling Specifications ispPAC20 CMR vs. Frequency 100 100 1k 10k 100k 1M Frequency (Hz) THD vs. Frequency (Gain=1) -40 Rload = 300 - ...
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... Typical Performance Characteristics 10.34kHz Filter F Accuracy C Large-Signal Response 1.0V Gain = 1 Load = No Load Large-Signal Response with 600pF Load Specifications ispPAC20 46.46kHz Filter F Accuracy C Small-Signal Response 1 S Small-Signal Response with 600pF Load 10 91.98kHz Filter F Accuracy C ...
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... PAC-Designer, a Windows-based design environment. PAC-Designer includes an AC simulator for design veri- fication prior to programming. The user can download the design to the ispPAC20 at any time via the device’s IEEE Standard 1149.1 (JTAG) compliant serial port directly from the parallel port using an ispDOWNLOAD™ ...
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... VREF Figure 3. Output VREF IAF Input Offset Auto-Calibration. A unique feature of the ispPAC20 is its ability to automatically calibrate itself to achieve very low offset error. This is done utilizing on- chip circuitry to perform an auto-calibration (auto-cal) 12 (Minus Input). The common IN- ...
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... With this feature, the degrada- tion of device offset performance that could occur over time and temperature is dramatically reduced. Specifi- cally, this means one PACblock of an ispPAC20 in a gain configuration of one is guaranteed to never have an input offset error greater than 1mV, after being auto-cali- brated ...
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... F about 330kHz when the gain is 10. Examining this transfer function shows the pole fre- quency is (1/2 )(2g 62pF, then 600kHz options for feedback capacitance, there are at least 120 poles between 10kHz and 100kHz. 14 Specifications ispPAC20 C Feedback Enable 1pF to 62pF IA1 ...
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... Attenuator . The PACblock architecture makes varia- tions possible on these two basic building blocks just described. An example uses summation to connect an input amplifier (IA2) in parallel with the feedback element V OUT1 ( shown in Figure 8. (OUT1) F Figure 8. PACblock A V IN1 15 Specifications ispPAC20 FB < IA1 R F OA1 IA2 2 ...
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... VREF Interfacing When used in a single-supply system where the system common mode voltage is near V directly connected to the ispPAC20 input. If the input disabled. F signal does not have such a DC bias, then one needs to be added to the signal in order to accommodate the input requirements for the ispPAC20 ...
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... VREF OUT Single-ended Operation Single-ended signals may be connected to the ispPAC20 input and one of the two differential ispPAC20 outputs can be used to drive single-ended circuitry. So, in addi- tion to fully differential I/O, either the input, output or both may be used single-ended. Single-ended Input . To connect the ispPAC20 differen- ...
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... Input Common-Mode Voltage Range For the ispPAC20, both maximum input signal range and corresponding common-mode voltage range are a func- tion of the input gain setting. The maximum input voltage times the gain of an individual PACblock cannot exceed the output range of that block or clipping will occur ...
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... JTAG/Direct : The DAC can be addressed directly, by- passing the E JTAG serial interface protocol. Using this serial address- ing mode retains the ability to reprogram the ispPAC20 DAC at any time without having to reconfigure the inter- face from one mode to another. SPI : The DAC can be addressed directly, bypassing the ...
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... Theory of Operation (Continued) Figure 12. ispPAC20 DAC Interface Options CS Serial Input Data Latches (pre-set to 80h at power-up) (4) TDI Serial DAC Input Shift Register (SR) TCK (2) DAC Address 2 E CMOS Memory CS(5) Parallel Input Data Latches (pre-set to 80h at power-up) DAC Parallel Input Data Pins D0-D7 Registers updated after JTAG command(s): ...
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... PACells are fully differential (true double- difference comparators). Both the plus and minus inputs of the ispPAC20 comparators have a Vin+ and a Vin- with cells transition to their the differential input voltage defined as [(Vin+) - (Vin-)]. This means the comparator output is high whenever the ...
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... PAC- Designer from a single gain setting listbox choice. With the ispPAC20 this is the case for IA1, IA2 and IA3. IA4 on the other hand, only has gain choices from - available in this particular dialog box. The reason is the ...
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... IA PACells is desired, the SRE bit associated with IA4 can be disabled by selecting the appropriated edit sym- bol command in PAC-Designer and making the change. Specifications ispPAC20 Description Always generates a +1 times whatever the gain setting of IA4 is. IA4 can be set to gains -10 in this mode. Display of the gain setting for IA4 in PAC-Designer is of the correct polarity ...
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... PAC-Designer software. See the online help associated with the ispPAC20 in PAC-Designer for more details of how to set/ program various operation modes. The list of control E bits available is given in Table 5. Specifications ispPAC20 Description Used to enable the serial, JTAG/Direct mode ...
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... Figure 13. PAC-Designer Design Entry Screen With Detailed Logic Schematic Diagram Specifications ispPAC20 25 ...
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... PAC-Designer environment. Full device programming is supported using PC parallel port I/O operations and a download cable connected to the serial programming interface of the ispPAC20. A library of configurations is included with basic solutions and examples of advanced circuit techniques. In addition, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer operation ...
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... SVF file which can be used with ispVM™ for embed- ded programming applications. By virtue of its standard interface, compatibility is maintained with existing pro- duction programming equipment giving customers a wide Figure 15. Configuring the ispPAC20 “In-System” from a PC Parallel Port PAC-Designer Software Specifications ispPAC20 degree of freedom and flexibility in production planning ...
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... TMS TRST TDI TCK Specifications ispPAC20 out of the user register to verify the current ispPAC20 configuration. Instructions exist to access all data regis- ters and perform internal control operations. For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. ...
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... In addition, there are several proprietary instructions that allow the device to be configured and verified. For ispPAC20, the instruction word length is 5- bits. All ispPAC20 instructions available to users are shown in Table 6. BYPASS is one of the three required instructions. It ...
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... Sample/Preload. Default to BYPASS. BYPASS 11111 Bypass (connect TDI to TDO). ispPAC20. The bit code of this instruction is defined to be all ones by the IEEE 1149.1 standard. The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The ispPAC20 has no boundary-scan register, so for compatibility it defaults to the BYPASS mode when- ever this instruction is received ...
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... The UBE is used to return all user bits to a zero state at the same time. A UBE usually Specifications ispPAC20 proceeds a PRGUSR operation, otherwise one to zero changes would not be implemented. It can also be used to erase all configuration information from a device and is the default condition of parts shipped from the factory ...
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... Pin 1 Top View 0.650 (16.51) 0.656 (16.66) 0.685 (17.40) 0.695 (17.65) Pin 1 Top View 10.00 BSC 12.00 BSC Specifications ispPAC20 44-Pin Plastic PLCC Dimensions in Inches MIN./MAX. 0.050 (1.27) BSC 0.165 (4.19) 0.180 (4.57) Seating Plane Coplanarity not to exceed 0.004 (.102) 44-Pin TQFP Dimensions in Millimeters MIN./MAX. ...