isppac20 Lattice Semiconductor Corp., isppac20 Datasheet - Page 19

• Manufacturer Part Number: isppac20
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

DAC PACell
The ispPAC20 contains an 8-bit, voltage output, digital-
to-analog converter (DAC) PACell with many unique
features and options. Interface modes are user select-
able and include a direct 8-bit parallel port, a serial JTAG
address mode, or serial SPI address mode. The output of
the DAC is fully differential, making it compatible with the
rest of the ispPAC20’s internal analog I/O. The DAC’s
voltage output is available via external pins as well as by
on-chip routing for optional internal connection to either
the comparator PACells or any of the instrument amplifier
input PACells.
DAC Data Input Coding
Data input to the DAC, whether in serial or parallel mode,
determines its output value. The coding of the DAC is in
straight binary and corresponds to input to output rela-
tionship shown in Table 2, DAC I/O. In all serial modes,
8 bits of data are clocked in with D0 (the LSB) being first
in the data stream and D7 (the MSB) being last.
DAC Address Modes
Addressing modes are controlled from within
PAC-Designer (options in the DAC port configuration
pop-up) and by two external pins (DMode and ENSPI).
Figure 12 diagrams the various input data paths used to
implement the various ispPAC20 DAC addressing modes.
Also included in the figure is a truth table of the user E
settings and input logic levels required to enable them. All
serial data input modes are 8 bits long and clocked in LSB
(D0) first.
Table 2. DAC I/O
Theory of Operation (Continued)
-Full Scale (-FS)
MS - 1LSB
Mid Scale (MS)
MS + 1LSB
+Full Scale (+FS)
LSB Step Size
+FS + 1LSB
DEC
127
128
129
160
192
224
255
32
64
96
0
Code
HEX
7F
A0
C0
E0
FF
00
20
40
60
80
81
x + 0.0117
Vout+ (V)
1.0000
1.3750
1.7500
2.1250
2.4883
2.5000
2.5117
2.8750
3.2500
3.6250
3.9883
4.0000
2
19
Nominal Voltage
The choice of addressing modes depends largely on
application needs, but the primary benefit of each ad-
dressing mode is as follows:
JTAG/E
configuration memory. The DAC input code can still be
changed, but only by reprogramming the E
JTAG command and subject to the maximum number of
programming cycles allowed. This is the preferred mode
to use when the DAC setting must be retained when
device power has been cycled off and then on again.
Parallel : This mode allows direct parallel update access
to the DAC. The DAC can be updated continuously
without affecting E
sues. The DAC E
programmed via serial JTAG commands directly from the
value stored in the parallel input data latches at any time,
if desired.
JTAG/Direct : The DAC can be addressed directly, by-
passing the E
JTAG serial interface protocol. Using this serial address-
ing mode retains the ability to reprogram the ispPAC20
DAC at any time without having to reconfigure the inter-
face from one mode to another.
SPI : The DAC can be addressed directly, bypassing the
E
interface protocol. The SPI serial interface is one of the
most widely used protocols for communication with mixed
signal devices of all types. While in the SPI addressing
mode, programming of the DAC E
is not possible.
2
configuration memory via an SPI compatible serial
2
: Power-up state of DAC is determined by E
Specifications ispPAC20
x - 0.0117
Vout- (V)
4.0000
3.6250
3.2500
2.8750
2.5117
2.5000
2.4883
2.1250
1.7500
1.3750
1.0117
1.0000
2
configuration memory via the standard
2
2
programming cycle endurance is-
configuration cells can still be
Vout (Vdiff)
-3.0000
-2.2500
-1.5000
-0.7500
-0.0234
0.0000
0.0234
0.7500
1.5000
2.2500
2.9766
0.0234
2.9766
2
configuration memory
2
memory via
2